mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 14:41:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
06efc122a0
14 changed files with 167 additions and 1479 deletions
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@ -89,7 +89,7 @@ tlbtab:
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#endif
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/* TLB-entry for OCM */
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
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/* TLB-entry for Local Configuration registers => peripherals */
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tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
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@ -25,6 +25,7 @@
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#include <command.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/ppc4xx-isram.h>
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#include <spd_sdram.h>
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#include "epld.h"
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@ -255,7 +256,7 @@ static int on_off( const char *s )
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************************************************************************/
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static void l2cache_disable(void)
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{
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mtdcr( l2_cache_cfg, 0 );
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mtdcr( L2_CACHE_CFG, 0 );
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}
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@ -265,24 +266,24 @@ static void l2cache_disable(void)
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************************************************************************/
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static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
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{
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mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
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mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
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mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
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mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
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mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
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mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
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while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
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while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */
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mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
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mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
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mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
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mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
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mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
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mtdcr( l2_cache_snp1, 0 );
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mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
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mtdcr( L2_CACHE_SNP1, 0 );
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__asm__ volatile ("sync"); /* msync */
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mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
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mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
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__asm__ volatile ("sync");
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}
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@ -294,7 +295,7 @@ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
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************************************************************************/
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static int l2cache_status(void)
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{
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return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
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return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
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}
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@ -32,13 +32,9 @@
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#include "pci405.h"
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#if defined(CONFIG_CMD_BSP)
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extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
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extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
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unsigned long get_dcr(unsigned short);
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/*
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* Command loadpci: wait for signal from host and boot image.
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@ -97,33 +93,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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} else {
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sprintf(addr, "%08x", *ptr);
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#if 0
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/*
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* Boot image
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*/
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if (*ptr & 0x00000001) {
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/*
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* Boot VxWorks image via bootvx
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*/
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addr[strlen(addr)-1] = '0';
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printf("\nBooting VxWorks-Image at addr 0x%s ...\n", addr);
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setenv("loadaddr", addr);
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local_args[0] = argv[0];
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local_args[1] = NULL;
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status = do_bootvx (cmdtp, 0, 1, local_args);
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} else {
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/*
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* Boot image via bootm (normally Linux)
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*/
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printf("\nBooting Image at addr 0x%s ...\n", addr);
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setenv("loadaddr", addr);
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local_args[0] = argv[0];
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local_args[1] = NULL;
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status = do_bootm (cmdtp, 0, 1, local_args);
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}
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#else
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/*
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* Boot image via bootm
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*/
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@ -133,7 +102,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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local_args[0] = argv[0];
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local_args[1] = NULL;
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status = do_bootm (cmdtp, 0, 1, local_args);
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#endif
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}
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return 0;
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@ -143,843 +111,4 @@ U_BOOT_CMD(
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"loadpci - Wait for pci-image and boot it\n",
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NULL
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);
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#endif
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#if 1 /* test-only */
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int do_getpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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unsigned int val;
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int i;
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printf("\nPCI Configuration Regs for PPC405GP:");
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for (i=0; i<0x64; i+=4) {
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pci_read_config_dword(PCIDEVID_405GP, i, &val);
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if (!(i % 0x10)) {
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printf("\n%02x: ", i);
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}
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printf("%08x ", val);
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}
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printf("\n");
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return 0;
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}
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U_BOOT_CMD(
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getpci, 1, 1, do_getpci,
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"getpci - Print own pci configuration registers\n",
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NULL
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);
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int do_setpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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unsigned int addr;
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unsigned int val;
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addr = simple_strtol (argv[1], NULL, 16);
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val = simple_strtol (argv[2], NULL, 16);
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printf("\nWriting %08x to PCI reg %08x.\n", val, addr);
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pci_write_config_dword(PCIDEVID_405GP, addr, val);
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return 0;
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}
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U_BOOT_CMD(
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setpci, 3, 1, do_setpci,
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"setpci - Set one pci configuration lword\n",
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"<addr> <val>\n"
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" - Write pci configuration lword <val> to <addr>.\n"
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);
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int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int i;
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printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
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for (i=0; i<=0x1e0; i++) {
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if (!(i % 0x8)) {
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printf("\n%04x ", i);
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}
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printf("%08lx ", get_dcr(i));
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}
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printf("\n");
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return 0;
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}
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U_BOOT_CMD(
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dumpdcr, 1, 1, do_dumpdcr,
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"dumpdcr - Dump all DCR registers\n",
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NULL
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);
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int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
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printf("\n%04x %08x ", 947, mfspr(947));
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printf("\n%04x %08x ", 9, mfspr(9));
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printf("\n%04x %08x ", 1014, mfspr(1014));
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printf("\n%04x %08x ", 1015, mfspr(1015));
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printf("\n%04x %08x ", 1010, mfspr(1010));
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printf("\n%04x %08x ", 957, mfspr(957));
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printf("\n%04x %08x ", 1008, mfspr(1008));
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printf("\n%04x %08x ", 1018, mfspr(1018));
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printf("\n%04x %08x ", 954, mfspr(954));
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printf("\n%04x %08x ", 950, mfspr(950));
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printf("\n%04x %08x ", 951, mfspr(951));
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printf("\n%04x %08x ", 981, mfspr(981));
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printf("\n%04x %08x ", 980, mfspr(980));
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printf("\n%04x %08x ", 982, mfspr(982));
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printf("\n%04x %08x ", 1012, mfspr(1012));
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printf("\n%04x %08x ", 1013, mfspr(1013));
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printf("\n%04x %08x ", 948, mfspr(948));
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printf("\n%04x %08x ", 949, mfspr(949));
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printf("\n%04x %08x ", 1019, mfspr(1019));
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printf("\n%04x %08x ", 979, mfspr(979));
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printf("\n%04x %08x ", 8, mfspr(8));
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printf("\n%04x %08x ", 945, mfspr(945));
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printf("\n%04x %08x ", 987, mfspr(987));
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printf("\n%04x %08x ", 287, mfspr(287));
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printf("\n%04x %08x ", 953, mfspr(953));
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printf("\n%04x %08x ", 955, mfspr(955));
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printf("\n%04x %08x ", 272, mfspr(272));
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printf("\n%04x %08x ", 273, mfspr(273));
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printf("\n%04x %08x ", 274, mfspr(274));
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printf("\n%04x %08x ", 275, mfspr(275));
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printf("\n%04x %08x ", 260, mfspr(260));
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printf("\n%04x %08x ", 276, mfspr(276));
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printf("\n%04x %08x ", 261, mfspr(261));
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printf("\n%04x %08x ", 277, mfspr(277));
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printf("\n%04x %08x ", 262, mfspr(262));
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printf("\n%04x %08x ", 278, mfspr(278));
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printf("\n%04x %08x ", 263, mfspr(263));
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printf("\n%04x %08x ", 279, mfspr(279));
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printf("\n%04x %08x ", 26, mfspr(26));
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printf("\n%04x %08x ", 27, mfspr(27));
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printf("\n%04x %08x ", 990, mfspr(990));
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printf("\n%04x %08x ", 991, mfspr(991));
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printf("\n%04x %08x ", 956, mfspr(956));
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printf("\n%04x %08x ", 284, mfspr(284));
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printf("\n%04x %08x ", 285, mfspr(285));
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printf("\n%04x %08x ", 986, mfspr(986));
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printf("\n%04x %08x ", 984, mfspr(984));
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printf("\n%04x %08x ", 256, mfspr(256));
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printf("\n%04x %08x ", 1, mfspr(1));
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printf("\n%04x %08x ", 944, mfspr(944));
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printf("\n");
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return 0;
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}
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U_BOOT_CMD(
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dumpspr, 1, 1, do_dumpspr,
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"dumpspr - Dump all SPR registers\n",
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||||
NULL
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||||
);
|
||||
|
||||
|
||||
#define PCI0_BRDGOPT1 0x4a
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#define plb0_acr 0x87
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|
||||
int do_getplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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unsigned short val;
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|
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printf("PLB0_ACR=%08lx\n", get_dcr(0x87));
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pci_read_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, &val);
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printf("PCI0_BRDGOPT1=%04x\n", val);
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printf("CCR0=%08x\n", mfspr(ccr0));
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||||
|
||||
return 0;
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||||
}
|
||||
U_BOOT_CMD(
|
||||
getplb, 1, 1, do_getplb,
|
||||
"getplb - Dump all plb arbiter registers\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
int do_setplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int my_acr;
|
||||
unsigned int my_brdgopt1;
|
||||
unsigned int my_ccr0;
|
||||
|
||||
my_acr = simple_strtol (argv[1], NULL, 16);
|
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my_brdgopt1 = simple_strtol (argv[2], NULL, 16);
|
||||
my_ccr0 = simple_strtol (argv[3], NULL, 16);
|
||||
|
||||
mtdcr(plb0_acr, my_acr);
|
||||
pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, my_brdgopt1);
|
||||
mtspr(ccr0, my_ccr0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
setplb, 4, 1, do_setplb,
|
||||
"setplb - Set all plb arbiter registers\n",
|
||||
"PLB0_ACR PCI0_BRDGOPT1 CCR0\n"
|
||||
" - Set all plb arbiter registers\n"
|
||||
);
|
||||
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* The following code is only for test purposes!!!!
|
||||
* Please ignore this ugly stuff!!!!!!!!!!!!!!!!!!!
|
||||
*
|
||||
***********************************************************************/
|
||||
|
||||
#define PCI_ADDR 0xc0000000
|
||||
|
||||
int do_writepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int size;
|
||||
unsigned int countmax;
|
||||
int i;
|
||||
int max;
|
||||
volatile unsigned long *ptr;
|
||||
volatile unsigned long val;
|
||||
int loopcount = 0;
|
||||
int test_pci_read = 0;
|
||||
int test_pci_cfg_write = 0;
|
||||
int test_sync = 0;
|
||||
int test_pci_pre_read = 0;
|
||||
|
||||
addr = simple_strtol (argv[1], NULL, 16);
|
||||
size = simple_strtol (argv[2], NULL, 16);
|
||||
countmax = simple_strtol (argv[3], NULL, 16);
|
||||
if (countmax == 0)
|
||||
countmax = 1000;
|
||||
|
||||
do_getplb(NULL, 0, 0, NULL);
|
||||
|
||||
#if 0
|
||||
out32r(PMM0LA, 0);
|
||||
out32r(PMM0PCILA, 0);
|
||||
out32r(PMM0PCIHA, 0);
|
||||
out32r(PMM0MA, 0);
|
||||
out32r(PMM1LA, PCI_ADDR);
|
||||
out32r(PMM1PCILA, addr & 0xff000000);
|
||||
out32r(PMM1PCIHA, 0x00000000);
|
||||
out32r(PMM1MA, 0xff000001);
|
||||
#endif
|
||||
|
||||
printf("PMM1LA =%08lx\n", in32r(PMM1LA));
|
||||
printf("PMM1MA =%08lx\n", in32r(PMM1MA));
|
||||
printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
|
||||
printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
|
||||
|
||||
addr = PCI_ADDR | (addr & 0x00ffffff);
|
||||
printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
|
||||
|
||||
max = size >> 2;
|
||||
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
val = *(ulong *)0x00000000;
|
||||
if (val & 0x00000008) {
|
||||
test_pci_pre_read = 1;
|
||||
printf("Running test with pre pci-memory-read access!\n");
|
||||
}
|
||||
if (val & 0x00000004) {
|
||||
test_sync = 1;
|
||||
printf("Running test with sync instruction!\n");
|
||||
}
|
||||
if (val & 0x00000001) {
|
||||
test_pci_read = 1;
|
||||
printf("Running test with pci-memory-read access!\n");
|
||||
}
|
||||
if (val & 0x00000002) {
|
||||
test_pci_cfg_write = 1;
|
||||
printf("Running test with pci-config-write access!\n");
|
||||
}
|
||||
|
||||
while (1) {
|
||||
|
||||
if (test_pci_pre_read) {
|
||||
/*
|
||||
* Read one value back
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
val = *ptr;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write some values to host via pci busmastering
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
for (i=0; i<max; i++) {
|
||||
*ptr++ = i;
|
||||
}
|
||||
|
||||
if (test_sync) {
|
||||
/*
|
||||
* Sync previous writes
|
||||
*/
|
||||
ppcSync();
|
||||
}
|
||||
|
||||
if (test_pci_read) {
|
||||
/*
|
||||
* Read one value back
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
val = *ptr;
|
||||
}
|
||||
|
||||
if (test_pci_cfg_write) {
|
||||
/*
|
||||
* Generate IRQ to host via config regs
|
||||
*/
|
||||
pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00);
|
||||
}
|
||||
|
||||
if (loopcount++ > countmax) {
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
putc('.');
|
||||
|
||||
loopcount = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writepci, 4, 1, do_writepci,
|
||||
"writepci - Write some data to pcibus\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
#define PCI_CFGADDR 0xeec00000
|
||||
#define PCI_CFGDATA 0xeec00004
|
||||
|
||||
int ibmPciConfigWrite
|
||||
(
|
||||
int offset, /* offset into the configuration space */
|
||||
int width, /* data width */
|
||||
unsigned int data /* data to be written */
|
||||
)
|
||||
{
|
||||
/*
|
||||
* Write config register address to the PCI config address register
|
||||
* bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
|
||||
*/
|
||||
out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
|
||||
|
||||
#if 0 /* test-only */
|
||||
ppcSync();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Write value to be written to the PCI config data register
|
||||
*/
|
||||
switch ( width ) {
|
||||
case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
|
||||
break;
|
||||
case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
|
||||
break;
|
||||
case 4: out32r(PCI_CFGDATA | (offset & 0x3), data);
|
||||
break;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int do_writepci2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int size;
|
||||
unsigned int countmax;
|
||||
int max;
|
||||
volatile unsigned long *ptr;
|
||||
volatile unsigned long val;
|
||||
int loopcount = 0;
|
||||
|
||||
addr = simple_strtol (argv[1], NULL, 16);
|
||||
size = simple_strtol (argv[2], NULL, 16);
|
||||
countmax = simple_strtol (argv[3], NULL, 16);
|
||||
if (countmax == 0)
|
||||
countmax = 1000;
|
||||
|
||||
do_getplb(NULL, 0, 0, NULL);
|
||||
|
||||
#if 0
|
||||
out32r(PMM0LA, 0);
|
||||
out32r(PMM0PCILA, 0);
|
||||
out32r(PMM0PCIHA, 0);
|
||||
out32r(PMM0MA, 0);
|
||||
out32r(PMM1LA, PCI_ADDR);
|
||||
out32r(PMM1PCILA, addr & 0xff000000);
|
||||
out32r(PMM1PCIHA, 0x00000000);
|
||||
out32r(PMM1MA, 0xff000001);
|
||||
#endif
|
||||
|
||||
printf("PMM1LA =%08lx\n", in32r(PMM1LA));
|
||||
printf("PMM1MA =%08lx\n", in32r(PMM1MA));
|
||||
printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
|
||||
printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
|
||||
|
||||
addr = PCI_ADDR | (addr & 0x00ffffff);
|
||||
printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
|
||||
|
||||
max = size >> 2;
|
||||
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
while (1) {
|
||||
|
||||
/*
|
||||
* Write one values to host via pci busmastering
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
*ptr = 0x01234567;
|
||||
|
||||
/*
|
||||
* Read one value back
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
val = *ptr;
|
||||
|
||||
/*
|
||||
* One pci config write
|
||||
*/
|
||||
/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
|
||||
/* ibmPciConfigWrite(0x44, 1, 0x00); */
|
||||
ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
|
||||
|
||||
if (loopcount++ > countmax) {
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
putc('.');
|
||||
|
||||
loopcount = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writepci2, 4, 1, do_writepci2,
|
||||
"writepci2- Write some data to pcibus\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int size;
|
||||
unsigned int countmax = 0;
|
||||
volatile unsigned long *ptr;
|
||||
volatile unsigned long val;
|
||||
|
||||
addr = simple_strtol (argv[1], NULL, 16);
|
||||
size = simple_strtol (argv[2], NULL, 16);
|
||||
|
||||
addr = PCI_ADDR | (addr & 0x00ffffff);
|
||||
printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
while (1) {
|
||||
|
||||
/*
|
||||
* Write one values to host via pci busmastering
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
*ptr = 0x01234567;
|
||||
|
||||
/*
|
||||
* Read one value back
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
val = *ptr;
|
||||
|
||||
/*
|
||||
* One pci config write
|
||||
*/
|
||||
ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writepci22, 4, 1, do_writepci22,
|
||||
"writepci22- Write some data to pcibus\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
int ibmPciConfigWrite3
|
||||
(
|
||||
int offset, /* offset into the configuration space */
|
||||
int width, /* data width */
|
||||
unsigned int data /* data to be written */
|
||||
)
|
||||
{
|
||||
/*
|
||||
* Write config register address to the PCI config address register
|
||||
* bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
|
||||
*/
|
||||
out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
|
||||
|
||||
#if 1 /* test-only */
|
||||
ppcSync();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Write value to be written to the PCI config data register
|
||||
*/
|
||||
switch ( width ) {
|
||||
case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
|
||||
break;
|
||||
case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
|
||||
break;
|
||||
case 4: out32r(PCI_CFGDATA | (offset & 0x3), data);
|
||||
break;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int size;
|
||||
unsigned int countmax;
|
||||
int max;
|
||||
volatile unsigned long *ptr;
|
||||
volatile unsigned long val;
|
||||
int loopcount = 0;
|
||||
|
||||
addr = simple_strtol (argv[1], NULL, 16);
|
||||
size = simple_strtol (argv[2], NULL, 16);
|
||||
countmax = simple_strtol (argv[3], NULL, 16);
|
||||
if (countmax == 0)
|
||||
countmax = 1000;
|
||||
|
||||
do_getplb(NULL, 0, 0, NULL);
|
||||
|
||||
#if 0
|
||||
out32r(PMM0LA, 0);
|
||||
out32r(PMM0PCILA, 0);
|
||||
out32r(PMM0PCIHA, 0);
|
||||
out32r(PMM0MA, 0);
|
||||
out32r(PMM1LA, PCI_ADDR);
|
||||
out32r(PMM1PCILA, addr & 0xff000000);
|
||||
out32r(PMM1PCIHA, 0x00000000);
|
||||
out32r(PMM1MA, 0xff000001);
|
||||
#endif
|
||||
|
||||
printf("PMM1LA =%08lx\n", in32r(PMM1LA));
|
||||
printf("PMM1MA =%08lx\n", in32r(PMM1MA));
|
||||
printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
|
||||
printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
|
||||
|
||||
addr = PCI_ADDR | (addr & 0x00ffffff);
|
||||
printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
|
||||
|
||||
max = size >> 2;
|
||||
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
while (1) {
|
||||
|
||||
/*
|
||||
* Write one values to host via pci busmastering
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
*ptr = 0x01234567;
|
||||
|
||||
/*
|
||||
* Read one value back
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
val = *ptr;
|
||||
|
||||
/*
|
||||
* One pci config write
|
||||
*/
|
||||
/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
|
||||
/* ibmPciConfigWrite(0x44, 1, 0x00); */
|
||||
ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
|
||||
|
||||
if (loopcount++ > countmax) {
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
putc('.');
|
||||
|
||||
loopcount = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writepci3, 4, 1, do_writepci3,
|
||||
"writepci3- Write some data to pcibus\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
|
||||
#define SECTOR_SIZE 32 /* 32 byte cache line */
|
||||
#define SECTOR_MASK 0x1F
|
||||
|
||||
void my_flush_dcache(ulong lcl_addr, ulong count)
|
||||
{
|
||||
unsigned int lcl_target;
|
||||
|
||||
/* promote to nearest cache sector */
|
||||
lcl_target = (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK;
|
||||
lcl_addr &= ~SECTOR_MASK;
|
||||
while (lcl_addr != lcl_target)
|
||||
{
|
||||
/* ppcDcbf((void *)lcl_addr);*/
|
||||
__asm__("dcbf 0,%0": :"r" (lcl_addr));
|
||||
lcl_addr += SECTOR_SIZE;
|
||||
}
|
||||
__asm__("sync"); /* Always flush prefetch queue in any case */
|
||||
}
|
||||
|
||||
int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int size;
|
||||
unsigned int countmax;
|
||||
int i;
|
||||
volatile unsigned long *ptr;
|
||||
volatile unsigned long val;
|
||||
int loopcount = 0;
|
||||
|
||||
addr = simple_strtol (argv[1], NULL, 16);
|
||||
size = simple_strtol (argv[2], NULL, 16);
|
||||
countmax = simple_strtol (argv[3], NULL, 16);
|
||||
if (countmax == 0)
|
||||
countmax = 1000;
|
||||
|
||||
do_getplb(NULL, 0, 0, NULL);
|
||||
|
||||
#if 0
|
||||
out32r(PMM0LA, 0);
|
||||
out32r(PMM0PCILA, 0);
|
||||
out32r(PMM0PCIHA, 0);
|
||||
out32r(PMM0MA, 0);
|
||||
out32r(PMM1LA, PCI_ADDR);
|
||||
out32r(PMM1PCILA, addr & 0xff000000);
|
||||
out32r(PMM1PCIHA, 0x00000000);
|
||||
out32r(PMM1MA, 0xff000001);
|
||||
#endif
|
||||
|
||||
printf("PMM1LA =%08lx\n", in32r(PMM1LA));
|
||||
printf("PMM1MA =%08lx\n", in32r(PMM1MA));
|
||||
printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
|
||||
printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
|
||||
|
||||
addr = PCI_ADDR | (addr & 0x00ffffff);
|
||||
printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
|
||||
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
i = 0;
|
||||
|
||||
/*
|
||||
* Set pci region as cachable
|
||||
*/
|
||||
ppcSync();
|
||||
__asm__ volatile (" addis 4,0,0x0000 ");
|
||||
__asm__ volatile (" addi 4,4,0x0080 ");
|
||||
__asm__ volatile (" mtdccr 4 ");
|
||||
ppcSync();
|
||||
|
||||
while (1) {
|
||||
|
||||
/*
|
||||
* Write one values to host via pci busmastering
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
printf("A\n"); /* test-only */
|
||||
*ptr++ = i++;
|
||||
*ptr++ = i++;
|
||||
*ptr++ = i++;
|
||||
*ptr++ = i++;
|
||||
*ptr++ = i++;
|
||||
*ptr++ = i++;
|
||||
*ptr++ = i++;
|
||||
*ptr++ = i++;
|
||||
printf("B\n"); /* test-only */
|
||||
my_flush_dcache(addr, 32);
|
||||
printf("C\n"); /* test-only */
|
||||
|
||||
/*
|
||||
* Read one value back
|
||||
*/
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
val = *ptr;
|
||||
printf("D\n"); /* test-only */
|
||||
|
||||
/*
|
||||
* One pci config write
|
||||
*/
|
||||
/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
|
||||
/* ibmPciConfigWrite(0x44, 1, 0x00); */
|
||||
ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
|
||||
printf("E\n"); /* test-only */
|
||||
|
||||
if (loopcount++ > countmax) {
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
putc('.');
|
||||
|
||||
loopcount = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writepci_cache, 4, 1, do_writepci_cache,
|
||||
"writepci_cache - Write some data to pcibus\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int *ptr;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Save own pci configuration in PRAM
|
||||
*/
|
||||
memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
|
||||
ptr = (unsigned int *)PCI_REGS_ADDR + 1;
|
||||
for (i=0; i<0x40; i+=4) {
|
||||
pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
|
||||
}
|
||||
ptr = (unsigned int *)PCI_REGS_ADDR;
|
||||
*ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
|
||||
|
||||
printf("\nStoring PCI Configuration Regs...\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
savepci, 4, 1, do_savepci,
|
||||
"savepci - Save all pci regs\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int *ptr;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Rewrite pci config regs (only after soft-reset with magic set)
|
||||
*/
|
||||
ptr = (unsigned int *)PCI_REGS_ADDR;
|
||||
if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
|
||||
puts("Restoring PCI Configurations Regs!\n");
|
||||
ptr = (unsigned int *)PCI_REGS_ADDR + 1;
|
||||
for (i=0; i<0x40; i+=4) {
|
||||
pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
|
||||
}
|
||||
}
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
restorepci, 4, 1, do_restorepci,
|
||||
"restorepci - Restore all pci regs\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
|
||||
extern void write_without_sync(void);
|
||||
extern void write_with_sync(void);
|
||||
extern void write_with_less_sync(void);
|
||||
extern void write_with_more_sync(void);
|
||||
|
||||
/*
|
||||
* code from IBM-PPCSUPP
|
||||
*/
|
||||
int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
write_without_sync();
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writeibm1, 4, 1, do_writeibm1,
|
||||
"writeibm1- Write some data to pcibus (without sync)\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
write_with_sync();
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writeibm2, 4, 1, do_writeibm2,
|
||||
"writeibm2- Write some data to pcibus (with sync)\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
write_with_less_sync();
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writeibm22, 4, 1, do_writeibm22,
|
||||
"writeibm22- Write some data to pcibus (with less sync)\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
|
||||
int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
|
||||
|
||||
write_with_more_sync();
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
writeibm3, 4, 1, do_writeibm3,
|
||||
"writeibm3- Write some data to pcibus (with more sync)\n",
|
||||
"<addr> <size>\n"
|
||||
" - Write some data to pcibus.\n"
|
||||
);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <malloc.h>
|
||||
#include <pci.h>
|
||||
#include <asm/4xx_pci.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "pci405.h"
|
||||
|
||||
|
|
@ -34,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
/* Prototypes */
|
||||
int gunzip(void *, int, unsigned char *, unsigned long *);
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
unsigned long fpga_done_state(void);
|
||||
unsigned long fpga_init_state(void);
|
||||
|
||||
|
|
@ -57,11 +58,11 @@ const unsigned char fpgadata[] =
|
|||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
|
||||
#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
|
||||
#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
|
||||
#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
|
||||
|
||||
#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
|
||||
#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
|
||||
#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
|
||||
#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
|
||||
|
||||
|
||||
int board_revision(void)
|
||||
|
|
@ -78,10 +79,10 @@ int board_revision(void)
|
|||
*/
|
||||
cntrl0Reg = mfdcr(cntrl0);
|
||||
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
|
||||
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
|
||||
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
|
||||
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
|
||||
udelay(1000); /* wait some time before reading input */
|
||||
value = in32(GPIO0_IR) & 0x00100200; /* get config bits */
|
||||
value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
|
||||
|
||||
/*
|
||||
* Restore GPIO settings
|
||||
|
|
@ -137,10 +138,10 @@ int board_early_init_f (void)
|
|||
/*
|
||||
* First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
|
||||
*/
|
||||
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
|
||||
out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
|
||||
out32(GPIO0_OR, 0); /* pull prg low */
|
||||
out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
|
||||
out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
|
||||
out_be32((void*)GPIO0_OR, 0); /* pull prg low */
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
|
|
@ -181,15 +182,6 @@ int board_early_init_f (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int misc_init_f (void)
|
||||
{
|
||||
return 0; /* dummy implementation */
|
||||
}
|
||||
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned char *dst;
|
||||
|
|
@ -284,13 +276,11 @@ int misc_init_r (void)
|
|||
*magic = 0; /* clear pci reconfig magic again */
|
||||
}
|
||||
|
||||
#if 1 /* test-only */
|
||||
/*
|
||||
* Decrease PLB latency timeout and reduce priority of the PCI bridge master
|
||||
*/
|
||||
#define PCI0_BRDGOPT1 0x4a
|
||||
pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
|
||||
/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */
|
||||
|
||||
#define plb0_acr 0x87
|
||||
/*
|
||||
|
|
@ -298,14 +288,6 @@ int misc_init_r (void)
|
|||
*/
|
||||
mtdcr(plb0_acr, 0x98000000);
|
||||
|
||||
#if 0 /* test-only */
|
||||
printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
|
||||
/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */
|
||||
mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
|
||||
#endif
|
||||
/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
|
||||
#endif
|
||||
|
||||
free(dst);
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -314,7 +296,6 @@ int misc_init_r (void)
|
|||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
|
|
@ -340,10 +321,10 @@ int checkboard (void)
|
|||
*/
|
||||
cntrl0Reg = mfdcr(cntrl0);
|
||||
mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
|
||||
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
|
||||
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
|
||||
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
|
||||
udelay(1000); /* wait some time before reading input */
|
||||
value = in32(GPIO0_IR) & 0x40000000; /* get config bits */
|
||||
value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
|
||||
if (value) {
|
||||
puts(", 33 MHz PCI");
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -63,7 +63,6 @@ SECTIONS
|
|||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
drivers/net/4xx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
|
|
|
|||
|
|
@ -1,55 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
if [ $# -ne 1 ]
|
||||
then
|
||||
echo "usage: Ltypes filename" >&2
|
||||
exit 2
|
||||
fi
|
||||
|
||||
FILE="$1"
|
||||
#TMPFILE='mktemp "${FILE}.XXXXXX"' || exit 1
|
||||
TMPFILE=${FILE}.`date "+%s"`
|
||||
touch $TMPFILE || exit 1
|
||||
|
||||
# Change all the Xilinx types to Linux types and put the result into a temp file
|
||||
sed \
|
||||
-e 's/\bXTRUE\b/TRUE/g' \
|
||||
-e 's/\bXFALSE\b/FALSE/g' \
|
||||
-e 's/\bXNULL\b/NULL/g' \
|
||||
-e 's/"xenv.h"/<asm\/delay.h>/g' \
|
||||
-e 's/\bXENV_USLEEP\b/udelay/g' \
|
||||
-e 's/\bXuint8\b/u8/g' \
|
||||
-e 's/\bXuint16\b/u16/g' \
|
||||
-e 's/\bXuint32\b/u32/g' \
|
||||
-e 's/\bXint8\b/s8/g' \
|
||||
-e 's/\bXint16\b/s16/g' \
|
||||
-e 's/\bXint32\b/s32/g' \
|
||||
-e 's/\bXboolean\b/u32/g' \
|
||||
"${FILE}" > "${TMPFILE}"
|
||||
|
||||
# Overlay the original file with the temp file
|
||||
mv "${TMPFILE}" "${FILE}"
|
||||
|
||||
# Are we doing xbasic_types.h?
|
||||
if [ "${FILE##*/}" = xbasic_types.h ]
|
||||
then
|
||||
# Remember as you're reading this that we've already gone through the prior
|
||||
# sed script. We need to do some other things to xbasic_types.h:
|
||||
# 1) Add ifndefs around TRUE and FALSE defines
|
||||
# 2) Remove definition of NULL as NULL
|
||||
# 3) Replace most of the primitive types section with a #include
|
||||
sed \
|
||||
-e '/u32 true/,/#define false/Ic\
|
||||
#ifndef TRUE\
|
||||
#define TRUE 1\
|
||||
#endif\
|
||||
#ifndef FALSE\
|
||||
#define FALSE 0\
|
||||
#endif' \
|
||||
-e '/#define[[:space:]][[:space:]]*NULL[[:space:]][[:space:]]*NULL/d' \
|
||||
-e '/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*char[[:space:]][[:space:]]*u8/,/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*long[[:space:]][[:space:]]*u32.*boolean/c\
|
||||
#include <linux/types.h>' \
|
||||
"${FILE}" > "${TMPFILE}"
|
||||
|
||||
mv "${TMPFILE}" "${FILE}"
|
||||
fi
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
# (c) Copyright 2004 Xilinx Inc.
|
||||
# Author: Xilinx, Inc.
|
||||
#
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the
|
||||
# Free Software Foundation; either version 2 of the License, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
|
||||
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
|
||||
# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
|
||||
# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
|
||||
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
|
||||
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
|
||||
# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
|
||||
# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
|
||||
# FITNESS FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
#
|
||||
# Xilinx hardware products are not intended for use in life support
|
||||
# appliances, devices, or systems. Use in such applications is
|
||||
# expressly prohibited.
|
||||
#
|
||||
#
|
||||
# (c) Copyright 2002-2004 Xilinx Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License along
|
||||
# with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
# 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN LIBRARY uboot OPTION DRC = uboot_drc;
|
||||
|
||||
BEGIN ARRAY connected_periphs PROPERTY desc = "Peripherals connected to U-Boot";
|
||||
PROPERTY size = 0;
|
||||
PARAM name = periph_name, desc = "Name of Peripheral connected", type = string;
|
||||
END ARRAY
|
||||
PARAMETER name = TARGET_DIR, desc = "Target Directory for U-Boot BSP", type = string;
|
||||
|
||||
# location of persistent storage in the IIC EEPROM (defaults are set for ML300)
|
||||
PARAMETER name = IIC_PERSISTENT_BASEADDR, desc = "Start of persistent storage block in the EEPROM address space", type = int, default = 1024;
|
||||
PARAMETER name = IIC_PERSISTENT_HIGHADDR, desc = "End of persistent storage block in the EEPROM address space", type = int, default = 2047;
|
||||
PARAMETER name = IIC_PERSISTENT_EEPROMADDR, desc = "Address of the EEPROM on the IIC bus", type = int, default = 0xA0;
|
||||
|
||||
END LIBRARY
|
||||
|
|
@ -1,325 +0,0 @@
|
|||
#
|
||||
# Author: Xilinx, Inc.
|
||||
#
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the
|
||||
# Free Software Foundation; either version 2 of the License, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
|
||||
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
|
||||
# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
|
||||
# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
|
||||
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
|
||||
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
|
||||
# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
|
||||
# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
|
||||
# FITNESS FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
#
|
||||
# Xilinx hardware products are not intended for use in life support
|
||||
# appliances, devices, or systems. Use in such applications is
|
||||
# expressly prohibited.
|
||||
#
|
||||
#
|
||||
# (c) Copyright 2002-2004 Xilinx Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License along
|
||||
# with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
# 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
#
|
||||
# Globals
|
||||
lappend drvlist
|
||||
set ltypes "../../../sw_services/uboot_v1_00_a/data/Ltypes"
|
||||
|
||||
proc uboot_drc {lib_handle} {
|
||||
puts "U-Boot DRC..."
|
||||
}
|
||||
|
||||
proc generate {libname} {
|
||||
|
||||
global drvlist
|
||||
|
||||
# Get list of peripherals connected to uboot
|
||||
set conn_periphs [xget_handle $libname "ARRAY" "connected_periphs"]
|
||||
#lappend drvlist
|
||||
if {[string compare -nocase $conn_periphs ""] != 0} {
|
||||
set conn_periphs_elems [xget_handle $conn_periphs "ELEMENTS" "*"]
|
||||
# For each periph
|
||||
foreach periph_elem $conn_periphs_elems {
|
||||
set periph [xget_value $periph_elem "PARAMETER" "periph_name"]
|
||||
# 1. Get driver
|
||||
set drv [xget_swhandle $periph]
|
||||
set posn [lsearch -exact $drvlist $drv]
|
||||
if {$posn == -1} {
|
||||
lappend drvlist $drv
|
||||
}
|
||||
}
|
||||
|
||||
set file_handle [xopen_include_file "xparameters.h"]
|
||||
puts $file_handle "\n/******************************************************************/\n"
|
||||
puts $file_handle "/* U-Boot Redefines */"
|
||||
puts $file_handle "\n/******************************************************************/\n"
|
||||
close $file_handle
|
||||
|
||||
foreach drv $drvlist {
|
||||
set drvname [xget_value $drv "NAME"]
|
||||
|
||||
#Redefines xparameters.h
|
||||
if {[string compare -nocase $drvname "uartns550"] == 0} {
|
||||
xredefine_uartns550 $drv "xparameters.h"
|
||||
} elseif {[string compare -nocase $drvname "emac"] == 0} {
|
||||
xredefine_emac $drv "xparameters.h"
|
||||
} elseif {[string compare -nocase $drvname "iic"] == 0} {
|
||||
xredefine_iic $drv "xparameters.h"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# define core_clock
|
||||
xredefine_params $libname "xparameters.h" "CORE_CLOCK_FREQ_HZ"
|
||||
|
||||
# define the values for the persistent storage in IIC
|
||||
xredefine_params $libname "xparameters.h" "IIC_PERSISTENT_BASEADDR" "IIC_PERSISTENT_HIGHADDR" "IIC_PERSISTENT_EEPROMADDR"
|
||||
|
||||
}
|
||||
|
||||
proc xget_corefreq {} {
|
||||
set processor [xget_processor]
|
||||
set name [xget_value $processor "NAME"]
|
||||
puts "procname : $name"
|
||||
set processor_driver [xget_swhandle [xget_value $processor "NAME"]]
|
||||
puts "procdrv : $processor_driver"
|
||||
if {[string compare -nocase $processor_driver ""] != 0} {
|
||||
set arg "CORE_CLOCK_FREQ_HZ"
|
||||
#set retval [xget_value $processor_driver "PARAMETER" $arg]
|
||||
set retval [xget_dname [xget_value $processor_driver "NAME"] $arg]
|
||||
return $retval
|
||||
}
|
||||
}
|
||||
|
||||
# procedure that adds # defines to xparameters.h as XPAR_argument
|
||||
proc xredefine_params {handle file_name args} {
|
||||
|
||||
puts "xredfine ..."
|
||||
# Open include file
|
||||
set file_handle [xopen_include_file $file_name]
|
||||
puts "args : $args"
|
||||
|
||||
foreach arg $args {
|
||||
if {[string compare -nocase $arg "CORE_CLOCK_FREQ_HZ"] == 0} {
|
||||
set value [xget_corefreq]
|
||||
puts "corefreq : $value"
|
||||
} else {
|
||||
set value [xget_value $handle "PARAMETER" $arg]
|
||||
puts "value : $value"
|
||||
}
|
||||
|
||||
if {$value != ""} {
|
||||
set value [xformat_addr_string $value $arg]
|
||||
|
||||
if {[string compare -nocase $arg "IIC_PERSISTENT_BASEADDR"] == 0} {
|
||||
set name "PERSISTENT_0_IIC_0_BASEADDR"
|
||||
} elseif {[string compare -nocase $arg "IIC_PERSISTENT_HIGHADDR"] == 0} {
|
||||
set name "PERSISTENT_0_IIC_0_HIGHADDR"
|
||||
} elseif {[string compare -nocase $arg "IIC_PERSISTENT_EEPROMADDR"] == 0} {
|
||||
set name "PERSISTENT_0_IIC_0_EEPROMADDR"
|
||||
} else {
|
||||
set name [string toupper $arg]
|
||||
}
|
||||
set name [format "XPAR_%s" $name]
|
||||
puts $file_handle "#define $name $value"
|
||||
}
|
||||
}
|
||||
|
||||
puts $file_handle "\n/******************************************************************/\n"
|
||||
close $file_handle
|
||||
}
|
||||
|
||||
# uart redefines...
|
||||
proc xredefine_uartns550 {drvhandle file_name} {
|
||||
|
||||
xredefine_include_file $drvhandle $file_name "uartns550" "C_BASEADDR" "C_HIGHADDR" "CLOCK_HZ" "DEVICE_ID"
|
||||
|
||||
}
|
||||
|
||||
proc xredefine_emac {drvhandle file_name} {
|
||||
|
||||
xredefine_include_file $drvhandle $file_name "emac" "C_BASEADDR" "C_HIGHADDR" "C_DMA_PRESENT" "C_MII_EXIST" "C_ERR_COUNT_EXIST" "DEVICE_ID"
|
||||
|
||||
}
|
||||
|
||||
proc xredefine_iic {drvhandle file_name} {
|
||||
xredefine_include_file $drvhandle $file_name "iic" "C_BASEADDR" "C_HIGHADDR" "C_TEN_BIT_ADR" "DEVICE_ID"
|
||||
|
||||
}
|
||||
|
||||
#######################
|
||||
|
||||
proc xredefine_include_file {drv_handle file_name drv_string args} {
|
||||
|
||||
# Open include file
|
||||
set file_handle [xopen_include_file $file_name]
|
||||
|
||||
# Get all peripherals connected to this driver
|
||||
set periphs [xget_periphs $drv_handle]
|
||||
|
||||
set pname [format "XPAR_%s_" [string toupper $drv_string]]
|
||||
|
||||
# Print all parameters for all peripherals
|
||||
set device_id 0
|
||||
set sub_periphs 1
|
||||
foreach periph $periphs {
|
||||
puts "$periph : $drv_string : $sub_periphs"
|
||||
|
||||
for {set i 0} {$i < $sub_periphs} {incr i} {
|
||||
foreach arg $args {
|
||||
set name "${pname}${device_id}_"
|
||||
|
||||
if {[string compare -nocase "CLOCK_HZ" $arg] == 0} {
|
||||
set xdrv_string [format "%s%s" "X" $drv_string]
|
||||
set value [xget_dname $xdrv_string $arg]
|
||||
set name "${name}CLOCK_FREQ_HZ"
|
||||
} else {
|
||||
if {[string match C_* $arg]} {
|
||||
set name [format "%s%s" $name [string range $arg 2 end]]
|
||||
} else {
|
||||
set name "${name}${arg}"
|
||||
}
|
||||
set value [xget_name $periph $arg]
|
||||
}
|
||||
|
||||
if {[string compare -nocase "uartns550" $drv_string] == 0} {
|
||||
if {[string compare -nocase "C_BASEADDR" $arg] == 0} {
|
||||
set value [format "(%s%s%s)" $value "+" "0x1000"]
|
||||
}
|
||||
}
|
||||
|
||||
puts $file_handle "#define $name $value"
|
||||
if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
|
||||
incr device_id
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
puts $file_handle "\n/******************************************************************/\n"
|
||||
close $file_handle
|
||||
}
|
||||
|
||||
##################################################
|
||||
# procedure post_generate
|
||||
# This generates the drivers directory for uboot
|
||||
# and runs the ltypes script
|
||||
##################################################
|
||||
|
||||
proc post_generate {lib_handle} {
|
||||
|
||||
global drvlist
|
||||
|
||||
# Create U-Boot tree structure
|
||||
set pwd [pwd]
|
||||
set common_dir "uboot/board/xilinx/common"
|
||||
set xilinx_enet_dir "uboot/board/xilinx/xilinx_enet"
|
||||
set ml300_dir "uboot/board/xilinx/ml300"
|
||||
|
||||
exec bash -c "mkdir -p $common_dir $xilinx_enet_dir $ml300_dir"
|
||||
|
||||
# Copy files for xilinx_ocp
|
||||
xcopy_commonfiles
|
||||
|
||||
foreach drv $drvlist {
|
||||
set drvname [xget_value $drv "NAME"]
|
||||
set ver [xget_value $drv "PARAMETER" "DRIVER_VER"]
|
||||
set ver [string map {. _} $ver]
|
||||
set dirname [format "%s_v%s" $drvname $ver]
|
||||
|
||||
if {[string compare -nocase $drvname "emac"] == 0} {
|
||||
xcopy_emac $drv $dirname
|
||||
} elseif {[string compare -nocase $drvname "iic"] == 0} {
|
||||
xcopy_iic $drv $dirname
|
||||
}
|
||||
}
|
||||
|
||||
# Call Ltypes Script here
|
||||
set uboot "uboot"
|
||||
xltype_file $uboot
|
||||
|
||||
# Move xparameters.h around
|
||||
exec bash -c "cp ../../include/xparameters.h $ml300_dir"
|
||||
|
||||
# copy the whole U-Boot BSP to its final destination
|
||||
set value [xget_value $lib_handle "PARAMETER" TARGET_DIR]
|
||||
puts "TARGET_DIR : $value"
|
||||
|
||||
if {$value != ""} {
|
||||
if {[file isdirectory $value] == 0} {
|
||||
exec bash -c "mkdir -p $value"
|
||||
}
|
||||
exec bash -c "cp -Rp uboot/* $value"
|
||||
}
|
||||
}
|
||||
|
||||
proc xcopy_commonfiles {} {
|
||||
|
||||
global drvlist
|
||||
|
||||
set common_dir "uboot/board/xilinx/common"
|
||||
|
||||
foreach drv $drvlist {
|
||||
set depends [xget_value $drv "OPTION" "DEPENDS"]
|
||||
foreach dep $depends {
|
||||
puts "dep : $dep"
|
||||
if {[file isdirectory "../$dep"] == 1} {
|
||||
exec bash -c "cp -f ../$dep/src/*.c $common_dir"
|
||||
exec bash -c "cp -f ../$dep/src/*.h $common_dir"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
proc xcopy_emac {drv_handle dirname} {
|
||||
set emac "board/xilinx/xilinx_enet"
|
||||
xcopy_dir $dirname $emac
|
||||
}
|
||||
|
||||
proc xcopy_iic {drv_handle dirname} {
|
||||
set iic "board/xilinx/xilinx_iic"
|
||||
xcopy_dir $dirname $iic
|
||||
}
|
||||
|
||||
proc xcopy_dir {srcdir dstdir} {
|
||||
|
||||
set dstdirname [format "%s%s" "uboot/" $dstdir]
|
||||
if {[file isdirectory "../$srcdir"] == 1} {
|
||||
# Copy files from src to dst
|
||||
exec bash -c "mkdir -p $dstdirname"
|
||||
exec bash -c "cp -f ../$srcdir/src/*.c $dstdirname"
|
||||
exec bash -c "cp -f ../$srcdir/src/*.h $dstdirname"
|
||||
} else {
|
||||
puts "$srcdir does not exist ..."
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc xltype_file {filename} {
|
||||
|
||||
global ltypes
|
||||
|
||||
puts $filename
|
||||
|
||||
if {[file isdirectory $filename]} {
|
||||
foreach entry [glob -nocomplain [file join $filename *]] {
|
||||
xltype_file $entry
|
||||
}
|
||||
} else {
|
||||
exec bash -c "$ltypes $filename"
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -72,6 +72,7 @@
|
|||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/ppc4xx-isram.h>
|
||||
|
||||
#ifndef CONFIG_IDENT_STRING
|
||||
#define CONFIG_IDENT_STRING ""
|
||||
|
|
@ -677,67 +678,80 @@ _start:
|
|||
/* not all PPC's have internal SRAM usable as L2-cache */
|
||||
#if defined(CONFIG_440GX) || \
|
||||
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
|
||||
defined(CONFIG_460SX)
|
||||
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
|
||||
mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
|
||||
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
lis r1, 0x0000
|
||||
ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
|
||||
mtdcr L2_CACHE_CFG,r1
|
||||
#endif
|
||||
|
||||
lis r2,0x7fff
|
||||
ori r2,r2,0xffff
|
||||
mfdcr r1,isram0_dpc
|
||||
mfdcr r1,ISRAM0_DPC
|
||||
and r1,r1,r2 /* Disable parity check */
|
||||
mtdcr isram0_dpc,r1
|
||||
mfdcr r1,isram0_pmeg
|
||||
mtdcr ISRAM0_DPC,r1
|
||||
mfdcr r1,ISRAM0_PMEG
|
||||
and r1,r1,r2 /* Disable pwr mgmt */
|
||||
mtdcr isram0_pmeg,r1
|
||||
mtdcr ISRAM0_PMEG,r1
|
||||
|
||||
lis r1,0x8000 /* BAS = 8000_0000 */
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
|
||||
ori r1,r1,0x0980 /* first 64k */
|
||||
mtdcr isram0_sb0cr,r1
|
||||
mtdcr ISRAM0_SB0CR,r1
|
||||
lis r1,0x8001
|
||||
ori r1,r1,0x0980 /* second 64k */
|
||||
mtdcr isram0_sb1cr,r1
|
||||
mtdcr ISRAM0_SB1CR,r1
|
||||
lis r1, 0x8002
|
||||
ori r1,r1, 0x0980 /* third 64k */
|
||||
mtdcr isram0_sb2cr,r1
|
||||
mtdcr ISRAM0_SB2CR,r1
|
||||
lis r1, 0x8003
|
||||
ori r1,r1, 0x0980 /* fourth 64k */
|
||||
mtdcr isram0_sb3cr,r1
|
||||
#elif defined(CONFIG_440SPE)
|
||||
lis r1,0x0000 /* BAS = 0000_0000 */
|
||||
mtdcr ISRAM0_SB3CR,r1
|
||||
#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
lis r1,0x0000 /* BAS = X_0000_0000 */
|
||||
ori r1,r1,0x0984 /* first 64k */
|
||||
mtdcr isram0_sb0cr,r1
|
||||
mtdcr ISRAM0_SB0CR,r1
|
||||
lis r1,0x0001
|
||||
ori r1,r1,0x0984 /* second 64k */
|
||||
mtdcr isram0_sb1cr,r1
|
||||
mtdcr ISRAM0_SB1CR,r1
|
||||
lis r1, 0x0002
|
||||
ori r1,r1, 0x0984 /* third 64k */
|
||||
mtdcr isram0_sb2cr,r1
|
||||
mtdcr ISRAM0_SB2CR,r1
|
||||
lis r1, 0x0003
|
||||
ori r1,r1, 0x0984 /* fourth 64k */
|
||||
mtdcr isram0_sb3cr,r1
|
||||
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
lis r1,0x4000 /* BAS = 8000_0000 */
|
||||
ori r1,r1,0x4580 /* 16k */
|
||||
mtdcr isram0_sb0cr,r1
|
||||
mtdcr ISRAM0_SB3CR,r1
|
||||
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
lis r2,0x7fff
|
||||
ori r2,r2,0xffff
|
||||
mfdcr r1,ISRAM1_DPC
|
||||
and r1,r1,r2 /* Disable parity check */
|
||||
mtdcr ISRAM1_DPC,r1
|
||||
mfdcr r1,ISRAM1_PMEG
|
||||
and r1,r1,r2 /* Disable pwr mgmt */
|
||||
mtdcr ISRAM1_PMEG,r1
|
||||
|
||||
lis r1,0x0004 /* BAS = 4_0004_0000 */
|
||||
ori r1,r1,0x0984 /* 64k */
|
||||
mtdcr ISRAM1_SB0CR,r1
|
||||
#endif
|
||||
#elif defined(CONFIG_460SX)
|
||||
lis r1,0x0000 /* BAS = 0000_0000 */
|
||||
ori r1,r1,0x0B84 /* first 128k */
|
||||
mtdcr isram0_sb0cr,r1
|
||||
mtdcr ISRAM0_SB0CR,r1
|
||||
lis r1,0x0001
|
||||
ori r1,r1,0x0B84 /* second 128k */
|
||||
mtdcr isram0_sb1cr,r1
|
||||
mtdcr ISRAM0_SB1CR,r1
|
||||
lis r1, 0x0002
|
||||
ori r1,r1, 0x0B84 /* third 128k */
|
||||
mtdcr isram0_sb2cr,r1
|
||||
mtdcr ISRAM0_SB2CR,r1
|
||||
lis r1, 0x0003
|
||||
ori r1,r1, 0x0B84 /* fourth 128k */
|
||||
mtdcr isram0_sb3cr,r1
|
||||
mtdcr ISRAM0_SB3CR,r1
|
||||
#elif defined(CONFIG_440GP)
|
||||
ori r1,r1,0x0380 /* 8k rw */
|
||||
mtdcr isram0_sb0cr,r1
|
||||
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
|
||||
mtdcr ISRAM0_SB0CR,r1
|
||||
mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
|
||||
#endif
|
||||
#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
|
||||
|
||||
|
|
@ -1440,6 +1454,10 @@ relocate_code:
|
|||
dccci 0,0 /* Invalidate data cache, now no longer our stack */
|
||||
sync
|
||||
isync
|
||||
|
||||
/* Clear all potential pending exceptions */
|
||||
mfspr r1,mcsr
|
||||
mtspr mcsr,r1
|
||||
#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
|
||||
addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
|
||||
#else
|
||||
|
|
|
|||
75
include/asm-ppc/ppc4xx-isram.h
Normal file
75
include/asm-ppc/ppc4xx-isram.h
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
|
||||
/*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _PPC4xx_ISRAM_H_
|
||||
#define _PPC4xx_ISRAM_H_
|
||||
|
||||
/*
|
||||
* Internal SRAM
|
||||
*/
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define ISRAM0_DCR_BASE 0x380
|
||||
#else
|
||||
#define ISRAM0_DCR_BASE 0x020
|
||||
#endif
|
||||
#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
|
||||
#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
|
||||
#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
|
||||
#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
|
||||
#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
|
||||
#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
|
||||
#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
|
||||
#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
|
||||
#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
|
||||
#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
|
||||
#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
|
||||
|
||||
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
#define ISRAM1_DCR_BASE 0x0B0
|
||||
#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
|
||||
#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
|
||||
#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
|
||||
#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
|
||||
#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
|
||||
#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
|
||||
#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
|
||||
#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
|
||||
#endif /* CONFIG_460EX || CONFIG_460GT */
|
||||
|
||||
/*
|
||||
* L2 Cache
|
||||
*/
|
||||
#if defined (CONFIG_440GX) || \
|
||||
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
|
||||
defined(CONFIG_460SX)
|
||||
#define L2_CACHE_BASE 0x030
|
||||
#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
|
||||
#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
|
||||
#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
|
||||
#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
|
||||
#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
|
||||
#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
|
||||
#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
|
||||
#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
|
||||
#endif /* CONFIG_440GX */
|
||||
|
||||
#endif /* _PPC4xx_ISRAM_H_ */
|
||||
|
|
@ -60,39 +60,24 @@
|
|||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
|
||||
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_ITEST
|
||||
#undef CONFIG_CMD_LOADB
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_NFS
|
||||
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
|
@ -102,7 +87,6 @@
|
|||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
|
|
@ -166,15 +150,9 @@
|
|||
#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
|
||||
#if 0 /* test-only */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
#else
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
|
|
@ -215,22 +193,10 @@
|
|||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#if 0 /* Use NVRAM for environment variables */
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
|
||||
#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
|
||||
|
||||
#else /* Use EEPROM for environment variables */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
|
||||
#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
|
||||
/* total size of a CAT24WC08 is 1024 bytes */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
|
||||
#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
|
||||
|
|
@ -327,14 +293,6 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
#if 0 /* test-only */
|
||||
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
#else
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
/* On Chip Memory location */
|
||||
|
|
@ -346,7 +304,6 @@
|
|||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@
|
|||
#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
|
||||
(u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
|
||||
|
||||
#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 16k */
|
||||
#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
|
||||
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
|
||||
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
|
||||
|
||||
|
|
|
|||
|
|
@ -53,6 +53,13 @@
|
|||
#define CONFIG_HOSTNAME katmai
|
||||
#include "amcc-common.h"
|
||||
|
||||
/*
|
||||
* For booting 256K-paged Linux we should have 16MB of memory
|
||||
* for Linux initial memory map
|
||||
*/
|
||||
#undef CONFIG_SYS_BOOTMAPSZ
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
|
|
@ -189,6 +196,7 @@
|
|||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
|
|
|||
|
|
@ -169,18 +169,9 @@
|
|||
#define sdr_ecid1 0x0081
|
||||
#define sdr_ecid2 0x0082
|
||||
#define sdr_jtag 0x00c0
|
||||
#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
|
||||
#define sdr_ddrdl 0x00e0
|
||||
#else
|
||||
#define sdr_cfg 0x00e0
|
||||
#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
|
||||
#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
|
||||
#define SDR_CFG_32BITS 0x00000000 /* 32 bits */
|
||||
#define SDR_CFG_64BITS 0x01000000 /* 64 bits */
|
||||
#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
|
||||
#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
|
||||
#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
|
||||
#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define SDR0_DDRCFG 0x00e0
|
||||
#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
|
||||
#define sdr_ebc 0x0100
|
||||
#define sdr_uart0 0x0120 /* UART0 Config */
|
||||
#define sdr_uart1 0x0121 /* UART1 Config */
|
||||
|
|
@ -616,45 +607,6 @@
|
|||
|
||||
#endif /* 440EP || 440GR || 440EPX || 440GRX */
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| L2 Cache
|
||||
+----------------------------------------------------------------------------*/
|
||||
#if defined (CONFIG_440GX) || \
|
||||
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
|
||||
defined(CONFIG_460SX)
|
||||
#define L2_CACHE_BASE 0x030
|
||||
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
|
||||
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
|
||||
#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
|
||||
#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
|
||||
#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
|
||||
#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
|
||||
#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
|
||||
#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
|
||||
|
||||
#endif /* CONFIG_440GX */
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| Internal SRAM
|
||||
+----------------------------------------------------------------------------*/
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define ISRAM0_DCR_BASE 0x380
|
||||
#else
|
||||
#define ISRAM0_DCR_BASE 0x020
|
||||
#endif
|
||||
#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
|
||||
#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
|
||||
#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
|
||||
#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
|
||||
#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
|
||||
#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
|
||||
#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
|
||||
#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
|
||||
#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
|
||||
#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
|
||||
#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue