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arm, davinci: Fix setting of the SDRAM configuration register

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da850_ddr_setup() expects the BOOTUNLOCK bit to be set in
If BOOTUNLOCK is not set in this define, several configuration
bits will not be writeable and the code will not work.

Since the BOOTUNLOCK and TIMUNLOCK bits are not configuration options
but access control bits, this patch changes the code to work
irrespective of the value of these bits in CONFIG_SYS_DA850_DDR2_SDBCR.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Christian Riesch 2011-11-08 08:55:13 -05:00 • committed by Sandeep Paulraj
parent 95c248f488
commit 085d4574c5
1 changed files with 19 additions and 6 deletions
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25
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
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@ -184,18 +184,31 @@ int da850_ddr_setup(unsigned int freq)
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_CMOSEN_BIT));
/*
* SDRAM Configuration Register (SDCR):
* First set the BOOTUNLOCK bit to make configuration bits
* writeable.
*/
setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
writel((CONFIG_SYS_DA850_DDR2_SDBCR & ~0xf0000000) |
(readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
&dv_ddr2_regs_ctrl->sdbcr);
writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
/*
* Write the new value of these bits and clear BOOTUNLOCK.
* At the same time, set the TIMUNLOCK bit to allow changing
* the timing registers
*/
tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
tmp &= ~(0x1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT);
tmp |= (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */
writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
/* clear the TIMUNLOCK bit and write the value of the CL field */
tmp &= ~(0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/*
* LPMODEN and MCLKSTOPEN must be set!