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- Add LS1027A, LS1018A, LS1017A support - Few updates related to usb, ls1012a, lx2160a
This commit is contained in:
Tom Rini
commit
0e0b303a67
10 changed files with 76 additions and 10 deletions
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@ -68,12 +68,18 @@ static void __secure ls1_deepsleep_irq_cfg(void)
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ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
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/*
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* Workaround: There is bug of register ippdexpcr1, when read it always
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* returns zero, so its value is saved to a scrachpad register to be
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* read, that is why we don't read it from register ippdexpcr1 itself.
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* Workaround of errata A-008646
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* Errata states that read to register ippdexpcr1 always returns
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* zero irrespective of what value is written into it. So its value
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* is first saved to a spare register and then read from it
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*/
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ippdexpcr1 = in_le32(&scfg->sparecr[7]);
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out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
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ippdexpcr1 = in_be32(&scfg->sparecr[7]);
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/*
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* To allow OCRAM to be used as wakeup source in deep sleep,
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* do not power it down.
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*/
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out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1);
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if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
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pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
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@ -59,6 +59,9 @@ static struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
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CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
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CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
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CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
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CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
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CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
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CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
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CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
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CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
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@ -401,6 +401,26 @@ void fdt_fixup_remove_jr(void *blob)
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}
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#endif
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#ifdef CONFIG_ARCH_LS1028A
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static void fdt_disable_multimedia(void *blob, unsigned int svr)
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{
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int off;
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if (IS_MULTIMEDIA_EN(svr))
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return;
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/* Disable eDP/LCD node */
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off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
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if (off != -FDT_ERR_NOTFOUND)
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fdt_status_disabled(blob, off);
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/* Disable GPU node */
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off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
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if (off != -FDT_ERR_NOTFOUND)
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fdt_status_disabled(blob, off);
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}
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#endif
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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@ -462,4 +482,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
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fdt_fixup_msi(blob);
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#endif
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#ifdef CONFIG_ARCH_LS1028A
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fdt_disable_multimedia(blob, svr);
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#endif
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}
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@ -627,10 +627,19 @@ void fsl_lsch2_early_init_f(void)
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#endif
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#endif
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/* Make SEC reads and writes snoopable */
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#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
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setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
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SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
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SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
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SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
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SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
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SCFG_SNPCNFGCR_SATAWRSNP);
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#else
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setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
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SCFG_SNPCNFGCR_SECWRSNP |
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SCFG_SNPCNFGCR_SATARDSNP |
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SCFG_SNPCNFGCR_SATAWRSNP);
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#endif
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/*
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* Enable snoop requests and DVM message requests for
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@ -409,6 +409,12 @@ struct ccsr_gur {
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#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
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#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
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#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
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#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
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#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
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#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
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#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
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#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
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#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
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/* RGMIIPCR bit definitions*/
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#define SCFG_RGMIIPCR_EN_AUTO BIT(3)
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP
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* Copyright 2017-2019 NXP
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* Copyright 2015 Freescale Semiconductor
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*/
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@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
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/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
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#define SVR_LS1043A_P23 0x879202
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#define SVR_LS1023A_P23 0x87920A
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#define SVR_LS1017A 0x870B24
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#define SVR_LS1018A 0x870B20
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#define SVR_LS1027A 0x870B04
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#define SVR_LS1028A 0x870B00
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#define SVR_LS1046A 0x870700
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#define SVR_LS1026A 0x870708
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@ -100,9 +103,9 @@ enum boot_src get_boot_src(void);
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#define SVR_LS2044A 0x870930
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#define SVR_LS2081A 0x870918
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#define SVR_LS2041A 0x870914
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#define SVR_LX2160A 0x873601
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#define SVR_LX2120A 0x873621
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#define SVR_LX2080A 0x873603
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#define SVR_LX2160A 0x873600
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#define SVR_LX2120A 0x873620
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#define SVR_LX2080A 0x873602
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#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
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#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
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@ -112,6 +115,9 @@ enum boot_src get_boot_src(void);
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#ifdef CONFIG_ARCH_LX2160A
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#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
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#endif
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#ifdef CONFIG_ARCH_LS1028A
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#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
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#endif
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#define IS_SVR_REV(svr, maj, min) \
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((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
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#define SVR_DEV(svr) ((svr) >> 8)
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@ -155,7 +155,7 @@ struct ccsr_gur {
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#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
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#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
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#define SCFG_PIXCLKCR_PXCKEN 0x80000000
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#define SCFG_QSPI_CLKSEL 0xc0100000
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#define SCFG_QSPI_CLKSEL 0x50100000
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#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
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#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
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#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000
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@ -63,6 +63,10 @@ int board_init(void)
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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@ -23,6 +23,11 @@
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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/* ENV */
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#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
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CONFIG_ENV_OFFSET)
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#ifndef CONFIG_SPL_BUILD
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#undef BOOT_TARGET_DEVICES
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#define BOOT_TARGET_DEVICES(func) \
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@ -17,6 +17,10 @@
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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/* ENV */
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#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
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CONFIG_ENV_OFFSET)
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/*
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* I2C IO expander
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*/
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