mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-net
This commit is contained in:
commit
0ee8746a93
28 changed files with 2252 additions and 1023 deletions
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@ -367,7 +367,6 @@ typedef struct {
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int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
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int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
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int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
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int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
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void davinci_eth_set_mac_addr(const u_int8_t *addr);
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typedef struct
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typedef struct
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{
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{
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@ -409,15 +409,6 @@ void start_armboot (void)
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enable_interrupts ();
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enable_interrupts ();
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/* Perform network card initialisation if necessary */
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/* Perform network card initialisation if necessary */
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#ifdef CONFIG_DRIVER_TI_EMAC
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/* XXX: this needs to be moved to board init */
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extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
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if (getenv ("ethaddr")) {
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uchar enetaddr[6];
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eth_getenv_enetaddr("ethaddr", enetaddr);
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davinci_eth_set_mac_addr(enetaddr);
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}
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#endif
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#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
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#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
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/* XXX: this needs to be moved to board init */
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/* XXX: this needs to be moved to board init */
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@ -821,16 +812,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
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enable_interrupts ();
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enable_interrupts ();
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/* Perform network card initialisation if necessary */
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/* Perform network card initialisation if necessary */
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#ifdef CONFIG_DRIVER_TI_EMAC
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/* XXX: this needs to be moved to board init */
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extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
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if (getenv ("ethaddr")) {
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uchar enetaddr[6];
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eth_getenv_enetaddr("ethaddr", enetaddr);
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davinci_eth_set_mac_addr(enetaddr);
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}
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#endif
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#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
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#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
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/* XXX: this needs to be moved to board init */
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/* XXX: this needs to be moved to board init */
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if (getenv ("ethaddr")) {
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if (getenv ("ethaddr")) {
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@ -85,45 +85,22 @@ err:
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return 0;
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return 0;
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}
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}
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/* If there is a MAC address in the environment, and if it is not identical to
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/*
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* the MAC address in the EEPROM, then a warning is printed and the MAC address
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* from the environment is used.
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*
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* If there is no MAC address in the environment, then it will be initialized
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* If there is no MAC address in the environment, then it will be initialized
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* (silently) from the value in the EEPROM.
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* (silently) from the value in the EEPROM.
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*/
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*/
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void dv_configure_mac_address(uint8_t *rom_enetaddr)
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void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
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{
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{
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int i;
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uint8_t env_enetaddr[6];
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u_int8_t env_enetaddr[6];
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char *tmp = getenv("ethaddr");
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char *end;
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/* Read Ethernet MAC address from the U-Boot environment.
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* If it is not defined, env_enetaddr[] will be cleared. */
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for (i = 0; i < 6; i++) {
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env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
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if (tmp)
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tmp = (*end) ? end+1 : end;
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}
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/* Check if EEPROM and U-Boot environment MAC addresses match. */
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if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
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memcmp(env_enetaddr, rom_enetaddr, 6) != 0) {
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printf("Warning: MAC addresses don't match:\n");
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printf(" EEPROM MAC address: %pM\n", rom_enetaddr);
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printf(" \"ethaddr\" value: %pM\n", env_enetaddr) ;
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debug("### Using MAC address from environment\n");
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}
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if (!tmp) {
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char ethaddr[20];
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eth_getenv_enetaddr_by_index(0, env_enetaddr);
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if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
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/* There is no MAC address in the environment, so we initialize
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/* There is no MAC address in the environment, so we initialize
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* it from the value in the EEPROM. */
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* it from the value in the EEPROM. */
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sprintf(ethaddr, "%pM", rom_enetaddr) ;
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debug("### Setting environment from EEPROM MAC address = "
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debug("### Setting environment from EEPROM MAC address = \"%s\"\n",
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"\"%pM\"\n",
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ethaddr);
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env_enetaddr);
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setenv("ethaddr", ethaddr);
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eth_setenv_enetaddr("ethaddr", rom_enetaddr);
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}
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}
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}
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}
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@ -46,7 +46,7 @@ struct pinmux_resource {
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}
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}
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int dvevm_read_mac_address(uint8_t *buf);
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int dvevm_read_mac_address(uint8_t *buf);
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void dv_configure_mac_address(uint8_t *rom_enetaddr);
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void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
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int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
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int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
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int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
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int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
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int n_items);
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int n_items);
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@ -196,19 +196,17 @@ int board_eth_init(bd_t *bis)
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{
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{
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u_int8_t mac_addr[6];
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u_int8_t mac_addr[6];
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u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
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u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
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struct eth_device *dev;
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/* Read Ethernet MAC address from EEPROM */
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/* Read Ethernet MAC address from EEPROM */
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if (dvevm_read_mac_address(mac_addr))
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if (dvevm_read_mac_address(mac_addr))
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/* set address env if not already set */
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/* set address env if not already set */
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dv_configure_mac_address(mac_addr);
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davinci_sync_env_enetaddr(mac_addr);
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/* read the address back from env */
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/* read the address back from env */
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if (!eth_getenv_enetaddr("ethaddr", mac_addr))
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if (!eth_getenv_enetaddr("ethaddr", mac_addr))
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return -1;
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return -1;
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/* provide the resulting addr to the driver */
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davinci_eth_set_mac_addr(mac_addr);
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/* enable the Ethernet switch in the 3 port PHY */
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/* enable the Ethernet switch in the 3 port PHY */
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if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
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if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
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switch_start_cmd, sizeof(switch_start_cmd))) {
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switch_start_cmd, sizeof(switch_start_cmd))) {
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@ -222,6 +220,12 @@ int board_eth_init(bd_t *bis)
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return -1;
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return -1;
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}
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}
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dev = eth_get_dev();
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/* provide the resulting addr to the driver */
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memcpy(dev->enetaddr, mac_addr, 6);
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dev->write_hwaddr(dev);
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return 0;
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return 0;
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}
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}
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#endif /* CONFIG_DRIVER_TI_EMAC */
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#endif /* CONFIG_DRIVER_TI_EMAC */
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@ -68,7 +68,7 @@ int board_eth_init(bd_t *bis)
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/* Read Ethernet MAC address from EEPROM */
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/* Read Ethernet MAC address from EEPROM */
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if (dvevm_read_mac_address(eeprom_enetaddr))
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if (dvevm_read_mac_address(eeprom_enetaddr))
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dv_configure_mac_address(eeprom_enetaddr);
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davinci_sync_env_enetaddr(eeprom_enetaddr);
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davinci_emac_initialize();
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davinci_emac_initialize();
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@ -71,7 +71,7 @@ int misc_init_r(void)
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/* Read Ethernet MAC address from EEPROM if available. */
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/* Read Ethernet MAC address from EEPROM if available. */
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if (dvevm_read_mac_address(eeprom_enetaddr))
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if (dvevm_read_mac_address(eeprom_enetaddr))
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dv_configure_mac_address(eeprom_enetaddr);
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davinci_sync_env_enetaddr(eeprom_enetaddr);
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i2c_read(0x39, 0x00, 1, &video_mode, 1);
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i2c_read(0x39, 0x00, 1, &video_mode, 1);
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@ -141,7 +141,7 @@ int misc_init_r(void)
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/* Read Ethernet MAC address from EEPROM if available. */
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/* Read Ethernet MAC address from EEPROM if available. */
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if (sffsdr_read_mac_address(eeprom_enetaddr))
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if (sffsdr_read_mac_address(eeprom_enetaddr))
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dv_configure_mac_address(eeprom_enetaddr);
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davinci_sync_env_enetaddr(eeprom_enetaddr);
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return(0);
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return(0);
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}
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}
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@ -70,7 +70,7 @@ int misc_init_r(void)
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/* Read Ethernet MAC address from EEPROM if available. */
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/* Read Ethernet MAC address from EEPROM if available. */
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if (dvevm_read_mac_address(eeprom_enetaddr))
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if (dvevm_read_mac_address(eeprom_enetaddr))
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dv_configure_mac_address(eeprom_enetaddr);
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davinci_sync_env_enetaddr(eeprom_enetaddr);
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return(0);
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return(0);
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}
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}
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@ -54,6 +54,7 @@ U_BOOT_CMD(
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"[loadAddress] [[hostIPaddr:]bootfilename]"
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"[loadAddress] [[hostIPaddr:]bootfilename]"
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);
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);
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|
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#ifdef CONFIG_CMD_RARP
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int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
|
{
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return netboot_common (RARP, cmdtp, argc, argv);
|
return netboot_common (RARP, cmdtp, argc, argv);
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|
@ -64,6 +65,7 @@ U_BOOT_CMD(
|
||||||
"boot image via network using RARP/TFTP protocol",
|
"boot image via network using RARP/TFTP protocol",
|
||||||
"[loadAddress] [[hostIPaddr:]bootfilename]"
|
"[loadAddress] [[hostIPaddr:]bootfilename]"
|
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);
|
);
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||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_DHCP)
|
#if defined(CONFIG_CMD_DHCP)
|
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int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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||||||
|
|
|
@ -40,6 +40,7 @@ COBJS-$(CONFIG_DNET) += dnet.o
|
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COBJS-$(CONFIG_E1000) += e1000.o
|
COBJS-$(CONFIG_E1000) += e1000.o
|
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COBJS-$(CONFIG_EEPRO100) += eepro100.o
|
COBJS-$(CONFIG_EEPRO100) += eepro100.o
|
||||||
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
|
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
|
||||||
|
COBJS-$(CONFIG_ENC28J60_LPC2292) += enc28j60_lpc2292.o
|
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COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
|
COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
|
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COBJS-$(CONFIG_ETHOC) += ethoc.o
|
COBJS-$(CONFIG_ETHOC) += ethoc.o
|
||||||
COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
|
COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
|
||||||
|
|
|
@ -208,7 +208,7 @@ static int at91emac_phy_reset(struct eth_device *netdev)
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at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
|
at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
|
||||||
(BMCR_ANENABLE | BMCR_ANRESTART));
|
(BMCR_ANENABLE | BMCR_ANRESTART));
|
||||||
|
|
||||||
for (i = 0; i < 100000 / 100; i++) {
|
for (i = 0; i < 30000; i++) {
|
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
||||||
MII_BMSR, &status);
|
MII_BMSR, &status);
|
||||||
if (status & BMSR_ANEGCOMPLETE)
|
if (status & BMSR_ANEGCOMPLETE)
|
||||||
|
@ -221,7 +221,7 @@ static int at91emac_phy_reset(struct eth_device *netdev)
|
||||||
} else {
|
} else {
|
||||||
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
|
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
|
||||||
netdev->name, status);
|
netdev->name, status);
|
||||||
return 1;
|
return -1;
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -240,7 +240,7 @@ static int at91emac_phy_init(struct eth_device *netdev)
|
||||||
MII_PHYSID1, &phy_id);
|
MII_PHYSID1, &phy_id);
|
||||||
if (phy_id == 0xffff) {
|
if (phy_id == 0xffff) {
|
||||||
printf("%s: No PHY present\n", netdev->name);
|
printf("%s: No PHY present\n", netdev->name);
|
||||||
return 1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
||||||
|
@ -249,7 +249,7 @@ static int at91emac_phy_init(struct eth_device *netdev)
|
||||||
if (!(status & BMSR_LSTATUS)) {
|
if (!(status & BMSR_LSTATUS)) {
|
||||||
/* Try to re-negotiate if we don't have link already. */
|
/* Try to re-negotiate if we don't have link already. */
|
||||||
if (at91emac_phy_reset(netdev))
|
if (at91emac_phy_reset(netdev))
|
||||||
return 2;
|
return -2;
|
||||||
|
|
||||||
for (i = 0; i < 100000 / 100; i++) {
|
for (i = 0; i < 100000 / 100; i++) {
|
||||||
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
||||||
|
@ -261,7 +261,7 @@ static int at91emac_phy_init(struct eth_device *netdev)
|
||||||
}
|
}
|
||||||
if (!(status & BMSR_LSTATUS)) {
|
if (!(status & BMSR_LSTATUS)) {
|
||||||
VERBOSEP("%s: link down\n", netdev->name);
|
VERBOSEP("%s: link down\n", netdev->name);
|
||||||
return 3;
|
return -3;
|
||||||
} else {
|
} else {
|
||||||
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
|
||||||
MII_ADVERTISE, &adv);
|
MII_ADVERTISE, &adv);
|
||||||
|
@ -286,7 +286,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
|
||||||
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
|
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
|
||||||
|
|
||||||
if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
|
if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
|
||||||
return 1;
|
return -1;
|
||||||
|
|
||||||
if (stat1 & BMSR_100FULL) {
|
if (stat1 & BMSR_100FULL) {
|
||||||
/*set Emac for 100BaseTX and Full Duplex */
|
/*set Emac for 100BaseTX and Full Duplex */
|
||||||
|
@ -321,7 +321,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
|
||||||
&emac->cfg);
|
&emac->cfg);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
return 1;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int at91emac_init(struct eth_device *netdev, bd_t *bd)
|
static int at91emac_init(struct eth_device *netdev, bd_t *bd)
|
||||||
|
@ -387,7 +387,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
|
||||||
at91emac_UpdateLinkSpeed(emac);
|
at91emac_UpdateLinkSpeed(emac);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
return 1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void at91emac_halt(struct eth_device *netdev)
|
static void at91emac_halt(struct eth_device *netdev)
|
||||||
|
@ -489,11 +489,11 @@ int at91emac_register(bd_t *bis, unsigned long iobase)
|
||||||
iobase = AT91_EMAC_BASE;
|
iobase = AT91_EMAC_BASE;
|
||||||
emac = malloc(sizeof(*emac)+512);
|
emac = malloc(sizeof(*emac)+512);
|
||||||
if (emac == NULL)
|
if (emac == NULL)
|
||||||
return 1;
|
return -1;
|
||||||
dev = malloc(sizeof(*dev));
|
dev = malloc(sizeof(*dev));
|
||||||
if (dev == NULL) {
|
if (dev == NULL) {
|
||||||
free(emac);
|
free(emac);
|
||||||
return 1;
|
return -1;
|
||||||
}
|
}
|
||||||
/* alignment as per Errata (64 bytes) is insufficient! */
|
/* alignment as per Errata (64 bytes) is insufficient! */
|
||||||
emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
|
emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
|
||||||
|
|
|
@ -65,21 +65,6 @@ void eth_mdio_enable(void)
|
||||||
davinci_eth_mdio_enable();
|
davinci_eth_mdio_enable();
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function must be called before emac_open() if you want to override
|
|
||||||
* the default mac address.
|
|
||||||
*/
|
|
||||||
void davinci_eth_set_mac_addr(const u_int8_t *addr)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < sizeof (davinci_eth_mac_addr); i++) {
|
|
||||||
davinci_eth_mac_addr[i] = addr[i];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* EMAC Addresses */
|
/* EMAC Addresses */
|
||||||
static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
|
static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
|
||||||
static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
|
static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
|
||||||
|
@ -100,6 +85,43 @@ static volatile u_int8_t active_phy_addr = 0xff;
|
||||||
|
|
||||||
phy_t phy;
|
phy_t phy;
|
||||||
|
|
||||||
|
static int davinci_eth_set_mac_addr(struct eth_device *dev)
|
||||||
|
{
|
||||||
|
unsigned long mac_hi;
|
||||||
|
unsigned long mac_lo;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
|
||||||
|
* receive)
|
||||||
|
* Using channel 0 only - other channels are disabled
|
||||||
|
* */
|
||||||
|
writel(0, &adap_emac->MACINDEX);
|
||||||
|
mac_hi = (dev->enetaddr[3] << 24) |
|
||||||
|
(dev->enetaddr[2] << 16) |
|
||||||
|
(dev->enetaddr[1] << 8) |
|
||||||
|
(dev->enetaddr[0]);
|
||||||
|
mac_lo = (dev->enetaddr[5] << 8) |
|
||||||
|
(dev->enetaddr[4]);
|
||||||
|
|
||||||
|
writel(mac_hi, &adap_emac->MACADDRHI);
|
||||||
|
#if defined(DAVINCI_EMAC_VERSION2)
|
||||||
|
writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
|
||||||
|
&adap_emac->MACADDRLO);
|
||||||
|
#else
|
||||||
|
writel(mac_lo, &adap_emac->MACADDRLO);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
writel(0, &adap_emac->MACHASH1);
|
||||||
|
writel(0, &adap_emac->MACHASH2);
|
||||||
|
|
||||||
|
/* Set source MAC address - REQUIRED */
|
||||||
|
writel(mac_hi, &adap_emac->MACSRCADDRHI);
|
||||||
|
writel(mac_lo, &adap_emac->MACSRCADDRLO);
|
||||||
|
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static void davinci_eth_mdio_enable(void)
|
static void davinci_eth_mdio_enable(void)
|
||||||
{
|
{
|
||||||
u_int32_t clkdiv;
|
u_int32_t clkdiv;
|
||||||
|
@ -286,8 +308,6 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
|
||||||
dv_reg_p addr;
|
dv_reg_p addr;
|
||||||
u_int32_t clkdiv, cnt;
|
u_int32_t clkdiv, cnt;
|
||||||
volatile emac_desc *rx_desc;
|
volatile emac_desc *rx_desc;
|
||||||
unsigned long mac_hi;
|
|
||||||
unsigned long mac_lo;
|
|
||||||
|
|
||||||
debug_emac("+ emac_open\n");
|
debug_emac("+ emac_open\n");
|
||||||
|
|
||||||
|
@ -311,30 +331,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
|
||||||
writel(1, &adap_emac->TXCONTROL);
|
writel(1, &adap_emac->TXCONTROL);
|
||||||
writel(1, &adap_emac->RXCONTROL);
|
writel(1, &adap_emac->RXCONTROL);
|
||||||
|
|
||||||
/* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
|
davinci_eth_set_mac_addr(dev);
|
||||||
/* Using channel 0 only - other channels are disabled */
|
|
||||||
writel(0, &adap_emac->MACINDEX);
|
|
||||||
mac_hi = (davinci_eth_mac_addr[3] << 24) |
|
|
||||||
(davinci_eth_mac_addr[2] << 16) |
|
|
||||||
(davinci_eth_mac_addr[1] << 8) |
|
|
||||||
(davinci_eth_mac_addr[0]);
|
|
||||||
mac_lo = (davinci_eth_mac_addr[5] << 8) |
|
|
||||||
(davinci_eth_mac_addr[4]);
|
|
||||||
|
|
||||||
writel(mac_hi, &adap_emac->MACADDRHI);
|
|
||||||
#if defined(DAVINCI_EMAC_VERSION2)
|
|
||||||
writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
|
|
||||||
&adap_emac->MACADDRLO);
|
|
||||||
#else
|
|
||||||
writel(mac_lo, &adap_emac->MACADDRLO);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
writel(0, &adap_emac->MACHASH1);
|
|
||||||
writel(0, &adap_emac->MACHASH2);
|
|
||||||
|
|
||||||
/* Set source MAC address - REQUIRED */
|
|
||||||
writel(mac_hi, &adap_emac->MACSRCADDRHI);
|
|
||||||
writel(mac_lo, &adap_emac->MACSRCADDRLO);
|
|
||||||
|
|
||||||
/* Set DMA 8 TX / 8 RX Head pointers to 0 */
|
/* Set DMA 8 TX / 8 RX Head pointers to 0 */
|
||||||
addr = &adap_emac->TX0HDP;
|
addr = &adap_emac->TX0HDP;
|
||||||
|
@ -636,6 +633,7 @@ int davinci_emac_initialize(void)
|
||||||
dev->halt = davinci_eth_close;
|
dev->halt = davinci_eth_close;
|
||||||
dev->send = davinci_eth_send_packet;
|
dev->send = davinci_eth_send_packet;
|
||||||
dev->recv = davinci_eth_rcv_packet;
|
dev->recv = davinci_eth_rcv_packet;
|
||||||
|
dev->write_hwaddr = davinci_eth_set_mac_addr;
|
||||||
|
|
||||||
eth_register(dev);
|
eth_register(dev);
|
||||||
|
|
||||||
|
|
File diff suppressed because it is too large
Load diff
251
drivers/net/enc28j60.h
Normal file
251
drivers/net/enc28j60.h
Normal file
|
@ -0,0 +1,251 @@
|
||||||
|
/*
|
||||||
|
* (X) extracted from enc28j60.c
|
||||||
|
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _enc28j60_h
|
||||||
|
#define _enc28j60_h
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPI Commands
|
||||||
|
*
|
||||||
|
* Bits 7-5: Command
|
||||||
|
* Bits 4-0: Register
|
||||||
|
*/
|
||||||
|
#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */
|
||||||
|
#define CMD_RBM 0x3a /* Read Buffer Memory */
|
||||||
|
#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */
|
||||||
|
#define CMD_WBM 0x7a /* Write Buffer Memory */
|
||||||
|
#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */
|
||||||
|
#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */
|
||||||
|
#define CMD_SRC 0xff /* System Reset Command */
|
||||||
|
|
||||||
|
/* NEW: encode (bank number+1) in upper byte */
|
||||||
|
|
||||||
|
/* Common Control Registers accessible in all Banks */
|
||||||
|
#define CTL_REG_EIE 0x01B
|
||||||
|
#define CTL_REG_EIR 0x01C
|
||||||
|
#define CTL_REG_ESTAT 0x01D
|
||||||
|
#define CTL_REG_ECON2 0x01E
|
||||||
|
#define CTL_REG_ECON1 0x01F
|
||||||
|
|
||||||
|
/* Control Registers accessible in Bank 0 */
|
||||||
|
#define CTL_REG_ERDPTL 0x100
|
||||||
|
#define CTL_REG_ERDPTH 0x101
|
||||||
|
#define CTL_REG_EWRPTL 0x102
|
||||||
|
#define CTL_REG_EWRPTH 0x103
|
||||||
|
#define CTL_REG_ETXSTL 0x104
|
||||||
|
#define CTL_REG_ETXSTH 0x105
|
||||||
|
#define CTL_REG_ETXNDL 0x106
|
||||||
|
#define CTL_REG_ETXNDH 0x107
|
||||||
|
#define CTL_REG_ERXSTL 0x108
|
||||||
|
#define CTL_REG_ERXSTH 0x109
|
||||||
|
#define CTL_REG_ERXNDL 0x10A
|
||||||
|
#define CTL_REG_ERXNDH 0x10B
|
||||||
|
#define CTL_REG_ERXRDPTL 0x10C
|
||||||
|
#define CTL_REG_ERXRDPTH 0x10D
|
||||||
|
#define CTL_REG_ERXWRPTL 0x10E
|
||||||
|
#define CTL_REG_ERXWRPTH 0x10F
|
||||||
|
#define CTL_REG_EDMASTL 0x110
|
||||||
|
#define CTL_REG_EDMASTH 0x111
|
||||||
|
#define CTL_REG_EDMANDL 0x112
|
||||||
|
#define CTL_REG_EDMANDH 0x113
|
||||||
|
#define CTL_REG_EDMADSTL 0x114
|
||||||
|
#define CTL_REG_EDMADSTH 0x115
|
||||||
|
#define CTL_REG_EDMACSL 0x116
|
||||||
|
#define CTL_REG_EDMACSH 0x117
|
||||||
|
|
||||||
|
/* Control Registers accessible in Bank 1 */
|
||||||
|
#define CTL_REG_EHT0 0x200
|
||||||
|
#define CTL_REG_EHT1 0x201
|
||||||
|
#define CTL_REG_EHT2 0x202
|
||||||
|
#define CTL_REG_EHT3 0x203
|
||||||
|
#define CTL_REG_EHT4 0x204
|
||||||
|
#define CTL_REG_EHT5 0x205
|
||||||
|
#define CTL_REG_EHT6 0x206
|
||||||
|
#define CTL_REG_EHT7 0x207
|
||||||
|
#define CTL_REG_EPMM0 0x208
|
||||||
|
#define CTL_REG_EPMM1 0x209
|
||||||
|
#define CTL_REG_EPMM2 0x20A
|
||||||
|
#define CTL_REG_EPMM3 0x20B
|
||||||
|
#define CTL_REG_EPMM4 0x20C
|
||||||
|
#define CTL_REG_EPMM5 0x20D
|
||||||
|
#define CTL_REG_EPMM6 0x20E
|
||||||
|
#define CTL_REG_EPMM7 0x20F
|
||||||
|
#define CTL_REG_EPMCSL 0x210
|
||||||
|
#define CTL_REG_EPMCSH 0x211
|
||||||
|
#define CTL_REG_EPMOL 0x214
|
||||||
|
#define CTL_REG_EPMOH 0x215
|
||||||
|
#define CTL_REG_EWOLIE 0x216
|
||||||
|
#define CTL_REG_EWOLIR 0x217
|
||||||
|
#define CTL_REG_ERXFCON 0x218
|
||||||
|
#define CTL_REG_EPKTCNT 0x219
|
||||||
|
|
||||||
|
/* Control Registers accessible in Bank 2 */
|
||||||
|
#define CTL_REG_MACON1 0x300
|
||||||
|
#define CTL_REG_MACON2 0x301
|
||||||
|
#define CTL_REG_MACON3 0x302
|
||||||
|
#define CTL_REG_MACON4 0x303
|
||||||
|
#define CTL_REG_MABBIPG 0x304
|
||||||
|
#define CTL_REG_MAIPGL 0x306
|
||||||
|
#define CTL_REG_MAIPGH 0x307
|
||||||
|
#define CTL_REG_MACLCON1 0x308
|
||||||
|
#define CTL_REG_MACLCON2 0x309
|
||||||
|
#define CTL_REG_MAMXFLL 0x30A
|
||||||
|
#define CTL_REG_MAMXFLH 0x30B
|
||||||
|
#define CTL_REG_MAPHSUP 0x30D
|
||||||
|
#define CTL_REG_MICON 0x311
|
||||||
|
#define CTL_REG_MICMD 0x312
|
||||||
|
#define CTL_REG_MIREGADR 0x314
|
||||||
|
#define CTL_REG_MIWRL 0x316
|
||||||
|
#define CTL_REG_MIWRH 0x317
|
||||||
|
#define CTL_REG_MIRDL 0x318
|
||||||
|
#define CTL_REG_MIRDH 0x319
|
||||||
|
|
||||||
|
/* Control Registers accessible in Bank 3 */
|
||||||
|
#define CTL_REG_MAADR1 0x400
|
||||||
|
#define CTL_REG_MAADR0 0x401
|
||||||
|
#define CTL_REG_MAADR3 0x402
|
||||||
|
#define CTL_REG_MAADR2 0x403
|
||||||
|
#define CTL_REG_MAADR5 0x404
|
||||||
|
#define CTL_REG_MAADR4 0x405
|
||||||
|
#define CTL_REG_EBSTSD 0x406
|
||||||
|
#define CTL_REG_EBSTCON 0x407
|
||||||
|
#define CTL_REG_EBSTCSL 0x408
|
||||||
|
#define CTL_REG_EBSTCSH 0x409
|
||||||
|
#define CTL_REG_MISTAT 0x40A
|
||||||
|
#define CTL_REG_EREVID 0x412
|
||||||
|
#define CTL_REG_ECOCON 0x415
|
||||||
|
#define CTL_REG_EFLOCON 0x417
|
||||||
|
#define CTL_REG_EPAUSL 0x418
|
||||||
|
#define CTL_REG_EPAUSH 0x419
|
||||||
|
|
||||||
|
/* PHY Register */
|
||||||
|
#define PHY_REG_PHCON1 0x00
|
||||||
|
#define PHY_REG_PHSTAT1 0x01
|
||||||
|
#define PHY_REG_PHID1 0x02
|
||||||
|
#define PHY_REG_PHID2 0x03
|
||||||
|
#define PHY_REG_PHCON2 0x10
|
||||||
|
#define PHY_REG_PHSTAT2 0x11
|
||||||
|
#define PHY_REG_PHLCON 0x14
|
||||||
|
|
||||||
|
/* Receive Filter Register (ERXFCON) bits */
|
||||||
|
#define ENC_RFR_UCEN 0x80
|
||||||
|
#define ENC_RFR_ANDOR 0x40
|
||||||
|
#define ENC_RFR_CRCEN 0x20
|
||||||
|
#define ENC_RFR_PMEN 0x10
|
||||||
|
#define ENC_RFR_MPEN 0x08
|
||||||
|
#define ENC_RFR_HTEN 0x04
|
||||||
|
#define ENC_RFR_MCEN 0x02
|
||||||
|
#define ENC_RFR_BCEN 0x01
|
||||||
|
|
||||||
|
/* ECON1 Register Bits */
|
||||||
|
#define ENC_ECON1_TXRST 0x80
|
||||||
|
#define ENC_ECON1_RXRST 0x40
|
||||||
|
#define ENC_ECON1_DMAST 0x20
|
||||||
|
#define ENC_ECON1_CSUMEN 0x10
|
||||||
|
#define ENC_ECON1_TXRTS 0x08
|
||||||
|
#define ENC_ECON1_RXEN 0x04
|
||||||
|
#define ENC_ECON1_BSEL1 0x02
|
||||||
|
#define ENC_ECON1_BSEL0 0x01
|
||||||
|
|
||||||
|
/* ECON2 Register Bits */
|
||||||
|
#define ENC_ECON2_AUTOINC 0x80
|
||||||
|
#define ENC_ECON2_PKTDEC 0x40
|
||||||
|
#define ENC_ECON2_PWRSV 0x20
|
||||||
|
#define ENC_ECON2_VRPS 0x08
|
||||||
|
|
||||||
|
/* EIR Register Bits */
|
||||||
|
#define ENC_EIR_PKTIF 0x40
|
||||||
|
#define ENC_EIR_DMAIF 0x20
|
||||||
|
#define ENC_EIR_LINKIF 0x10
|
||||||
|
#define ENC_EIR_TXIF 0x08
|
||||||
|
#define ENC_EIR_WOLIF 0x04
|
||||||
|
#define ENC_EIR_TXERIF 0x02
|
||||||
|
#define ENC_EIR_RXERIF 0x01
|
||||||
|
|
||||||
|
/* ESTAT Register Bits */
|
||||||
|
#define ENC_ESTAT_INT 0x80
|
||||||
|
#define ENC_ESTAT_LATECOL 0x10
|
||||||
|
#define ENC_ESTAT_RXBUSY 0x04
|
||||||
|
#define ENC_ESTAT_TXABRT 0x02
|
||||||
|
#define ENC_ESTAT_CLKRDY 0x01
|
||||||
|
|
||||||
|
/* EIE Register Bits */
|
||||||
|
#define ENC_EIE_INTIE 0x80
|
||||||
|
#define ENC_EIE_PKTIE 0x40
|
||||||
|
#define ENC_EIE_DMAIE 0x20
|
||||||
|
#define ENC_EIE_LINKIE 0x10
|
||||||
|
#define ENC_EIE_TXIE 0x08
|
||||||
|
#define ENC_EIE_WOLIE 0x04
|
||||||
|
#define ENC_EIE_TXERIE 0x02
|
||||||
|
#define ENC_EIE_RXERIE 0x01
|
||||||
|
|
||||||
|
/* MACON1 Register Bits */
|
||||||
|
#define ENC_MACON1_LOOPBK 0x10
|
||||||
|
#define ENC_MACON1_TXPAUS 0x08
|
||||||
|
#define ENC_MACON1_RXPAUS 0x04
|
||||||
|
#define ENC_MACON1_PASSALL 0x02
|
||||||
|
#define ENC_MACON1_MARXEN 0x01
|
||||||
|
|
||||||
|
/* MACON2 Register Bits */
|
||||||
|
#define ENC_MACON2_MARST 0x80
|
||||||
|
#define ENC_MACON2_RNDRST 0x40
|
||||||
|
#define ENC_MACON2_MARXRST 0x08
|
||||||
|
#define ENC_MACON2_RFUNRST 0x04
|
||||||
|
#define ENC_MACON2_MATXRST 0x02
|
||||||
|
#define ENC_MACON2_TFUNRST 0x01
|
||||||
|
|
||||||
|
/* MACON3 Register Bits */
|
||||||
|
#define ENC_MACON3_PADCFG2 0x80
|
||||||
|
#define ENC_MACON3_PADCFG1 0x40
|
||||||
|
#define ENC_MACON3_PADCFG0 0x20
|
||||||
|
#define ENC_MACON3_TXCRCEN 0x10
|
||||||
|
#define ENC_MACON3_PHDRLEN 0x08
|
||||||
|
#define ENC_MACON3_HFRMEN 0x04
|
||||||
|
#define ENC_MACON3_FRMLNEN 0x02
|
||||||
|
#define ENC_MACON3_FULDPX 0x01
|
||||||
|
|
||||||
|
/* MACON4 Register Bits */
|
||||||
|
#define ENC_MACON4_DEFER 0x40
|
||||||
|
|
||||||
|
/* MICMD Register Bits */
|
||||||
|
#define ENC_MICMD_MIISCAN 0x02
|
||||||
|
#define ENC_MICMD_MIIRD 0x01
|
||||||
|
|
||||||
|
/* MISTAT Register Bits */
|
||||||
|
#define ENC_MISTAT_NVALID 0x04
|
||||||
|
#define ENC_MISTAT_SCAN 0x02
|
||||||
|
#define ENC_MISTAT_BUSY 0x01
|
||||||
|
|
||||||
|
/* PHID1 and PHID2 values */
|
||||||
|
#define ENC_PHID1_VALUE 0x0083
|
||||||
|
#define ENC_PHID2_VALUE 0x1400
|
||||||
|
#define ENC_PHID2_MASK 0xFC00
|
||||||
|
|
||||||
|
/* PHCON1 values */
|
||||||
|
#define ENC_PHCON1_PDPXMD 0x0100
|
||||||
|
|
||||||
|
/* PHSTAT1 values */
|
||||||
|
#define ENC_PHSTAT1_LLSTAT 0x0004
|
||||||
|
|
||||||
|
/* PHSTAT2 values */
|
||||||
|
#define ENC_PHSTAT2_LSTAT 0x0400
|
||||||
|
#define ENC_PHSTAT2_DPXSTAT 0x0200
|
||||||
|
|
||||||
|
#endif
|
983
drivers/net/enc28j60_lpc2292.c
Normal file
983
drivers/net/enc28j60_lpc2292.c
Normal file
|
@ -0,0 +1,983 @@
|
||||||
|
/*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#warning This driver is depreciated. Please update to new SPI framework enc28j60 driver
|
||||||
|
#include <config.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <net.h>
|
||||||
|
#include <asm/arch/hardware.h>
|
||||||
|
#include <asm/arch/spi.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Control Registers in Bank 0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CTL_REG_ERDPTL 0x00
|
||||||
|
#define CTL_REG_ERDPTH 0x01
|
||||||
|
#define CTL_REG_EWRPTL 0x02
|
||||||
|
#define CTL_REG_EWRPTH 0x03
|
||||||
|
#define CTL_REG_ETXSTL 0x04
|
||||||
|
#define CTL_REG_ETXSTH 0x05
|
||||||
|
#define CTL_REG_ETXNDL 0x06
|
||||||
|
#define CTL_REG_ETXNDH 0x07
|
||||||
|
#define CTL_REG_ERXSTL 0x08
|
||||||
|
#define CTL_REG_ERXSTH 0x09
|
||||||
|
#define CTL_REG_ERXNDL 0x0A
|
||||||
|
#define CTL_REG_ERXNDH 0x0B
|
||||||
|
#define CTL_REG_ERXRDPTL 0x0C
|
||||||
|
#define CTL_REG_ERXRDPTH 0x0D
|
||||||
|
#define CTL_REG_ERXWRPTL 0x0E
|
||||||
|
#define CTL_REG_ERXWRPTH 0x0F
|
||||||
|
#define CTL_REG_EDMASTL 0x10
|
||||||
|
#define CTL_REG_EDMASTH 0x11
|
||||||
|
#define CTL_REG_EDMANDL 0x12
|
||||||
|
#define CTL_REG_EDMANDH 0x13
|
||||||
|
#define CTL_REG_EDMADSTL 0x14
|
||||||
|
#define CTL_REG_EDMADSTH 0x15
|
||||||
|
#define CTL_REG_EDMACSL 0x16
|
||||||
|
#define CTL_REG_EDMACSH 0x17
|
||||||
|
/* these are common in all banks */
|
||||||
|
#define CTL_REG_EIE 0x1B
|
||||||
|
#define CTL_REG_EIR 0x1C
|
||||||
|
#define CTL_REG_ESTAT 0x1D
|
||||||
|
#define CTL_REG_ECON2 0x1E
|
||||||
|
#define CTL_REG_ECON1 0x1F
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Control Registers in Bank 1
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CTL_REG_EHT0 0x00
|
||||||
|
#define CTL_REG_EHT1 0x01
|
||||||
|
#define CTL_REG_EHT2 0x02
|
||||||
|
#define CTL_REG_EHT3 0x03
|
||||||
|
#define CTL_REG_EHT4 0x04
|
||||||
|
#define CTL_REG_EHT5 0x05
|
||||||
|
#define CTL_REG_EHT6 0x06
|
||||||
|
#define CTL_REG_EHT7 0x07
|
||||||
|
#define CTL_REG_EPMM0 0x08
|
||||||
|
#define CTL_REG_EPMM1 0x09
|
||||||
|
#define CTL_REG_EPMM2 0x0A
|
||||||
|
#define CTL_REG_EPMM3 0x0B
|
||||||
|
#define CTL_REG_EPMM4 0x0C
|
||||||
|
#define CTL_REG_EPMM5 0x0D
|
||||||
|
#define CTL_REG_EPMM6 0x0E
|
||||||
|
#define CTL_REG_EPMM7 0x0F
|
||||||
|
#define CTL_REG_EPMCSL 0x10
|
||||||
|
#define CTL_REG_EPMCSH 0x11
|
||||||
|
#define CTL_REG_EPMOL 0x14
|
||||||
|
#define CTL_REG_EPMOH 0x15
|
||||||
|
#define CTL_REG_EWOLIE 0x16
|
||||||
|
#define CTL_REG_EWOLIR 0x17
|
||||||
|
#define CTL_REG_ERXFCON 0x18
|
||||||
|
#define CTL_REG_EPKTCNT 0x19
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Control Registers in Bank 2
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CTL_REG_MACON1 0x00
|
||||||
|
#define CTL_REG_MACON2 0x01
|
||||||
|
#define CTL_REG_MACON3 0x02
|
||||||
|
#define CTL_REG_MACON4 0x03
|
||||||
|
#define CTL_REG_MABBIPG 0x04
|
||||||
|
#define CTL_REG_MAIPGL 0x06
|
||||||
|
#define CTL_REG_MAIPGH 0x07
|
||||||
|
#define CTL_REG_MACLCON1 0x08
|
||||||
|
#define CTL_REG_MACLCON2 0x09
|
||||||
|
#define CTL_REG_MAMXFLL 0x0A
|
||||||
|
#define CTL_REG_MAMXFLH 0x0B
|
||||||
|
#define CTL_REG_MAPHSUP 0x0D
|
||||||
|
#define CTL_REG_MICON 0x11
|
||||||
|
#define CTL_REG_MICMD 0x12
|
||||||
|
#define CTL_REG_MIREGADR 0x14
|
||||||
|
#define CTL_REG_MIWRL 0x16
|
||||||
|
#define CTL_REG_MIWRH 0x17
|
||||||
|
#define CTL_REG_MIRDL 0x18
|
||||||
|
#define CTL_REG_MIRDH 0x19
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Control Registers in Bank 3
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CTL_REG_MAADR1 0x00
|
||||||
|
#define CTL_REG_MAADR0 0x01
|
||||||
|
#define CTL_REG_MAADR3 0x02
|
||||||
|
#define CTL_REG_MAADR2 0x03
|
||||||
|
#define CTL_REG_MAADR5 0x04
|
||||||
|
#define CTL_REG_MAADR4 0x05
|
||||||
|
#define CTL_REG_EBSTSD 0x06
|
||||||
|
#define CTL_REG_EBSTCON 0x07
|
||||||
|
#define CTL_REG_EBSTCSL 0x08
|
||||||
|
#define CTL_REG_EBSTCSH 0x09
|
||||||
|
#define CTL_REG_MISTAT 0x0A
|
||||||
|
#define CTL_REG_EREVID 0x12
|
||||||
|
#define CTL_REG_ECOCON 0x15
|
||||||
|
#define CTL_REG_EFLOCON 0x17
|
||||||
|
#define CTL_REG_EPAUSL 0x18
|
||||||
|
#define CTL_REG_EPAUSH 0x19
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PHY Register
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PHY_REG_PHID1 0x02
|
||||||
|
#define PHY_REG_PHID2 0x03
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
#define PHY_REG_PHCON1 0x00
|
||||||
|
#define PHY_REG_PHCON2 0x10
|
||||||
|
#define PHY_REG_PHLCON 0x14
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive Filter Register (ERXFCON) bits
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ENC_RFR_UCEN 0x80
|
||||||
|
#define ENC_RFR_ANDOR 0x40
|
||||||
|
#define ENC_RFR_CRCEN 0x20
|
||||||
|
#define ENC_RFR_PMEN 0x10
|
||||||
|
#define ENC_RFR_MPEN 0x08
|
||||||
|
#define ENC_RFR_HTEN 0x04
|
||||||
|
#define ENC_RFR_MCEN 0x02
|
||||||
|
#define ENC_RFR_BCEN 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ECON1 Register Bits
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ENC_ECON1_TXRST 0x80
|
||||||
|
#define ENC_ECON1_RXRST 0x40
|
||||||
|
#define ENC_ECON1_DMAST 0x20
|
||||||
|
#define ENC_ECON1_CSUMEN 0x10
|
||||||
|
#define ENC_ECON1_TXRTS 0x08
|
||||||
|
#define ENC_ECON1_RXEN 0x04
|
||||||
|
#define ENC_ECON1_BSEL1 0x02
|
||||||
|
#define ENC_ECON1_BSEL0 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ECON2 Register Bits
|
||||||
|
*/
|
||||||
|
#define ENC_ECON2_AUTOINC 0x80
|
||||||
|
#define ENC_ECON2_PKTDEC 0x40
|
||||||
|
#define ENC_ECON2_PWRSV 0x20
|
||||||
|
#define ENC_ECON2_VRPS 0x08
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EIR Register Bits
|
||||||
|
*/
|
||||||
|
#define ENC_EIR_PKTIF 0x40
|
||||||
|
#define ENC_EIR_DMAIF 0x20
|
||||||
|
#define ENC_EIR_LINKIF 0x10
|
||||||
|
#define ENC_EIR_TXIF 0x08
|
||||||
|
#define ENC_EIR_WOLIF 0x04
|
||||||
|
#define ENC_EIR_TXERIF 0x02
|
||||||
|
#define ENC_EIR_RXERIF 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ESTAT Register Bits
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ENC_ESTAT_INT 0x80
|
||||||
|
#define ENC_ESTAT_LATECOL 0x10
|
||||||
|
#define ENC_ESTAT_RXBUSY 0x04
|
||||||
|
#define ENC_ESTAT_TXABRT 0x02
|
||||||
|
#define ENC_ESTAT_CLKRDY 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EIE Register Bits
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ENC_EIE_INTIE 0x80
|
||||||
|
#define ENC_EIE_PKTIE 0x40
|
||||||
|
#define ENC_EIE_DMAIE 0x20
|
||||||
|
#define ENC_EIE_LINKIE 0x10
|
||||||
|
#define ENC_EIE_TXIE 0x08
|
||||||
|
#define ENC_EIE_WOLIE 0x04
|
||||||
|
#define ENC_EIE_TXERIE 0x02
|
||||||
|
#define ENC_EIE_RXERIE 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MACON1 Register Bits
|
||||||
|
*/
|
||||||
|
#define ENC_MACON1_LOOPBK 0x10
|
||||||
|
#define ENC_MACON1_TXPAUS 0x08
|
||||||
|
#define ENC_MACON1_RXPAUS 0x04
|
||||||
|
#define ENC_MACON1_PASSALL 0x02
|
||||||
|
#define ENC_MACON1_MARXEN 0x01
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MACON2 Register Bits
|
||||||
|
*/
|
||||||
|
#define ENC_MACON2_MARST 0x80
|
||||||
|
#define ENC_MACON2_RNDRST 0x40
|
||||||
|
#define ENC_MACON2_MARXRST 0x08
|
||||||
|
#define ENC_MACON2_RFUNRST 0x04
|
||||||
|
#define ENC_MACON2_MATXRST 0x02
|
||||||
|
#define ENC_MACON2_TFUNRST 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MACON3 Register Bits
|
||||||
|
*/
|
||||||
|
#define ENC_MACON3_PADCFG2 0x80
|
||||||
|
#define ENC_MACON3_PADCFG1 0x40
|
||||||
|
#define ENC_MACON3_PADCFG0 0x20
|
||||||
|
#define ENC_MACON3_TXCRCEN 0x10
|
||||||
|
#define ENC_MACON3_PHDRLEN 0x08
|
||||||
|
#define ENC_MACON3_HFRMEN 0x04
|
||||||
|
#define ENC_MACON3_FRMLNEN 0x02
|
||||||
|
#define ENC_MACON3_FULDPX 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MICMD Register Bits
|
||||||
|
*/
|
||||||
|
#define ENC_MICMD_MIISCAN 0x02
|
||||||
|
#define ENC_MICMD_MIIRD 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MISTAT Register Bits
|
||||||
|
*/
|
||||||
|
#define ENC_MISTAT_NVALID 0x04
|
||||||
|
#define ENC_MISTAT_SCAN 0x02
|
||||||
|
#define ENC_MISTAT_BUSY 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PHID1 and PHID2 values
|
||||||
|
*/
|
||||||
|
#define ENC_PHID1_VALUE 0x0083
|
||||||
|
#define ENC_PHID2_VALUE 0x1400
|
||||||
|
#define ENC_PHID2_MASK 0xFC00
|
||||||
|
|
||||||
|
|
||||||
|
#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
|
||||||
|
#define ENC_RESET 0x00020000 /* pin P1.17 */
|
||||||
|
|
||||||
|
#define FAILSAFE_VALUE 5000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Controller memory layout:
|
||||||
|
*
|
||||||
|
* 0x0000 - 0x17ff 6k bytes receive buffer
|
||||||
|
* 0x1800 - 0x1fff 2k bytes transmit buffer
|
||||||
|
*/
|
||||||
|
/* Use the lower memory for receiver buffer. See errata pt. 5 */
|
||||||
|
#define ENC_RX_BUF_START 0x0000
|
||||||
|
#define ENC_TX_BUF_START 0x1800
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
#define ENC_RX_BUF_END 0x17ff
|
||||||
|
#define ENC_TX_BUF_END 0x1fff
|
||||||
|
|
||||||
|
/* maximum frame length */
|
||||||
|
#define ENC_MAX_FRM_LEN 1518
|
||||||
|
|
||||||
|
#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
|
||||||
|
#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
|
||||||
|
#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
|
||||||
|
|
||||||
|
|
||||||
|
static unsigned char encReadReg (unsigned char regNo);
|
||||||
|
static void encWriteReg (unsigned char regNo, unsigned char data);
|
||||||
|
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
|
||||||
|
static void encReadBuff (unsigned short length, unsigned char *pBuff);
|
||||||
|
static void encWriteBuff (unsigned short length, unsigned char *pBuff);
|
||||||
|
static void encBitSet (unsigned char regNo, unsigned char data);
|
||||||
|
static void encBitClr (unsigned char regNo, unsigned char data);
|
||||||
|
static void encReset (void);
|
||||||
|
static void encInit (unsigned char *pEthAddr);
|
||||||
|
static unsigned short phyRead (unsigned char addr);
|
||||||
|
static void phyWrite(unsigned char, unsigned short);
|
||||||
|
static void encPoll (void);
|
||||||
|
static void encRx (void);
|
||||||
|
|
||||||
|
#define m_nic_read(reg) encReadReg(reg)
|
||||||
|
#define m_nic_write(reg, data) encWriteReg(reg, data)
|
||||||
|
#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
|
||||||
|
#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
|
||||||
|
#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
|
||||||
|
|
||||||
|
/* bit field set */
|
||||||
|
#define m_nic_bfs(reg, data) encBitSet(reg, data)
|
||||||
|
|
||||||
|
/* bit field clear */
|
||||||
|
#define m_nic_bfc(reg, data) encBitClr(reg, data)
|
||||||
|
|
||||||
|
static unsigned char bank = 0; /* current bank in enc28j60 */
|
||||||
|
static unsigned char next_pointer_lsb;
|
||||||
|
static unsigned char next_pointer_msb;
|
||||||
|
|
||||||
|
static unsigned char buffer[ENC_MAX_FRM_LEN];
|
||||||
|
static int rxResetCounter = 0;
|
||||||
|
|
||||||
|
#define RX_RESET_COUNTER 1000;
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
* Always returns 0
|
||||||
|
*/
|
||||||
|
int eth_init (bd_t * bis)
|
||||||
|
{
|
||||||
|
unsigned char estatVal;
|
||||||
|
uchar enetaddr[6];
|
||||||
|
|
||||||
|
/* configure GPIO */
|
||||||
|
(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
|
||||||
|
(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
|
||||||
|
|
||||||
|
/* CS and RESET active low */
|
||||||
|
PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
|
||||||
|
PUT32 (IO1SET, ENC_RESET);
|
||||||
|
|
||||||
|
spi_init ();
|
||||||
|
|
||||||
|
/* taken from the Linux driver - dangerous stuff here! */
|
||||||
|
/* Wait for CLKRDY to become set (i.e., check that we can communicate with
|
||||||
|
the ENC) */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
estatVal = m_nic_read(CTL_REG_ESTAT);
|
||||||
|
} while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
|
||||||
|
|
||||||
|
/* initialize controller */
|
||||||
|
encReset ();
|
||||||
|
eth_getenv_enetaddr("ethaddr", enetaddr);
|
||||||
|
encInit (enetaddr);
|
||||||
|
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int eth_send (volatile void *packet, int length)
|
||||||
|
{
|
||||||
|
/* check frame length, etc. */
|
||||||
|
/* TODO: */
|
||||||
|
|
||||||
|
/* switch to bank 0 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||||
|
|
||||||
|
/* set EWRPT */
|
||||||
|
m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
|
||||||
|
m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
|
||||||
|
|
||||||
|
/* set ETXND */
|
||||||
|
m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
|
||||||
|
m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
|
||||||
|
|
||||||
|
/* set ETXST */
|
||||||
|
m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
|
||||||
|
m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
|
||||||
|
|
||||||
|
/* write packet */
|
||||||
|
m_nic_write_data (length, (unsigned char *) packet);
|
||||||
|
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
/* Verify that the internal transmit logic has not been altered by excessive
|
||||||
|
collisions. See Errata B4 12 and 14.
|
||||||
|
*/
|
||||||
|
if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
|
||||||
|
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
|
||||||
|
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
|
||||||
|
}
|
||||||
|
m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
|
||||||
|
|
||||||
|
/* set ECON1.TXRTS */
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
* This function resets the receiver only. This function may be called from
|
||||||
|
* interrupt-context.
|
||||||
|
*/
|
||||||
|
static void encReceiverReset (void)
|
||||||
|
{
|
||||||
|
unsigned char econ1;
|
||||||
|
|
||||||
|
econ1 = m_nic_read (CTL_REG_ECON1);
|
||||||
|
if ((econ1 & ENC_ECON1_RXRST) == 0) {
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
|
||||||
|
rxResetCounter = RX_RESET_COUNTER;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
* receiver reset timer
|
||||||
|
*/
|
||||||
|
static void encReceiverResetCallback (void)
|
||||||
|
{
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
* Check for received packets. Call NetReceive for each packet. The return
|
||||||
|
* value is ignored by the caller.
|
||||||
|
*/
|
||||||
|
int eth_rx (void)
|
||||||
|
{
|
||||||
|
if (rxResetCounter > 0 && --rxResetCounter == 0) {
|
||||||
|
encReceiverResetCallback ();
|
||||||
|
}
|
||||||
|
|
||||||
|
encPoll ();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void eth_halt (void)
|
||||||
|
{
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*****************************************************************************/
|
||||||
|
|
||||||
|
static void encPoll (void)
|
||||||
|
{
|
||||||
|
unsigned char eir_reg;
|
||||||
|
volatile unsigned char estat_reg;
|
||||||
|
unsigned char pkt_cnt;
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ
|
||||||
|
/* clear global interrupt enable bit in enc28j60 */
|
||||||
|
m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||||
|
#endif
|
||||||
|
estat_reg = m_nic_read (CTL_REG_ESTAT);
|
||||||
|
|
||||||
|
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||||
|
|
||||||
|
if (eir_reg & ENC_EIR_TXIF) {
|
||||||
|
/* clear TXIF bit in EIR */
|
||||||
|
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
|
||||||
|
|
||||||
|
/* move to bank 1 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
|
||||||
|
/* read pktcnt */
|
||||||
|
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
|
||||||
|
|
||||||
|
if (pkt_cnt > 0) {
|
||||||
|
if ((eir_reg & ENC_EIR_PKTIF) == 0) {
|
||||||
|
/*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
|
||||||
|
}
|
||||||
|
encRx ();
|
||||||
|
/* clear PKTIF bit in EIR, this should not need to be done but it
|
||||||
|
seems like we get problems if we do not */
|
||||||
|
m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (eir_reg & ENC_EIR_RXERIF) {
|
||||||
|
printf ("encPoll: rx error\n");
|
||||||
|
m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
|
||||||
|
}
|
||||||
|
if (eir_reg & ENC_EIR_TXERIF) {
|
||||||
|
printf ("encPoll: tx error\n");
|
||||||
|
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ
|
||||||
|
/* set global interrupt enable bit in enc28j60 */
|
||||||
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encRx (void)
|
||||||
|
{
|
||||||
|
unsigned short pkt_len;
|
||||||
|
unsigned short copy_len;
|
||||||
|
unsigned short status;
|
||||||
|
unsigned char eir_reg;
|
||||||
|
unsigned char pkt_cnt = 0;
|
||||||
|
unsigned short rxbuf_rdpt;
|
||||||
|
|
||||||
|
/* switch to bank 0 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||||
|
|
||||||
|
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
||||||
|
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
||||||
|
|
||||||
|
do {
|
||||||
|
m_nic_read_data (6, buffer);
|
||||||
|
next_pointer_lsb = buffer[0];
|
||||||
|
next_pointer_msb = buffer[1];
|
||||||
|
pkt_len = buffer[2];
|
||||||
|
pkt_len |= (unsigned short) buffer[3] << 8;
|
||||||
|
status = buffer[4];
|
||||||
|
status |= (unsigned short) buffer[5] << 8;
|
||||||
|
|
||||||
|
if (pkt_len <= ENC_MAX_FRM_LEN)
|
||||||
|
copy_len = pkt_len;
|
||||||
|
else
|
||||||
|
copy_len = 0;
|
||||||
|
|
||||||
|
if ((status & (1L << 7)) == 0) /* check Received Ok bit */
|
||||||
|
copy_len = 0;
|
||||||
|
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
/* check if next pointer is resonable */
|
||||||
|
if ((((unsigned int)next_pointer_msb << 8) |
|
||||||
|
(unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
|
||||||
|
copy_len = 0;
|
||||||
|
|
||||||
|
if (copy_len > 0) {
|
||||||
|
m_nic_read_data (copy_len, buffer);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* advance read pointer to next pointer */
|
||||||
|
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
||||||
|
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
||||||
|
|
||||||
|
/* decrease packet counter */
|
||||||
|
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
|
||||||
|
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
/* Only odd values should be written to ERXRDPTL,
|
||||||
|
* see errata B4 pt.13
|
||||||
|
*/
|
||||||
|
rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
|
||||||
|
if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
|
||||||
|
m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
|
||||||
|
(m_nic_read(CTL_REG_ERXNDH) << 8 |
|
||||||
|
m_nic_read(CTL_REG_ERXNDL)))) {
|
||||||
|
m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
|
||||||
|
m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
|
||||||
|
} else {
|
||||||
|
m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
|
||||||
|
m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* move to bank 1 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
|
||||||
|
/* read pktcnt */
|
||||||
|
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
|
||||||
|
|
||||||
|
/* switch to bank 0 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1,
|
||||||
|
(ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||||
|
|
||||||
|
if (copy_len == 0) {
|
||||||
|
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||||
|
encReceiverReset ();
|
||||||
|
printf ("eth_rx: copy_len=0\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
NetReceive ((unsigned char *) buffer, pkt_len);
|
||||||
|
|
||||||
|
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||||
|
} while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encWriteReg (unsigned char regNo, unsigned char data)
|
||||||
|
{
|
||||||
|
spi_lock ();
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x40 | regNo); /* write in regNo */
|
||||||
|
spi_write (data);
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x1f); /* write reg 0x1f */
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
spi_unlock ();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
|
||||||
|
{
|
||||||
|
unsigned char readback;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
spi_lock ();
|
||||||
|
|
||||||
|
for (i = 0; i < c; i++) {
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x40 | regNo); /* write in regNo */
|
||||||
|
spi_write (data);
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x1f); /* write reg 0x1f */
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
|
||||||
|
spi_unlock (); /* we must unlock spi first */
|
||||||
|
|
||||||
|
readback = encReadReg (regNo);
|
||||||
|
|
||||||
|
spi_lock ();
|
||||||
|
|
||||||
|
if (readback == data)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
spi_unlock ();
|
||||||
|
|
||||||
|
if (i == c) {
|
||||||
|
printf ("enc28j60: write reg %d failed\n", regNo);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned char encReadReg (unsigned char regNo)
|
||||||
|
{
|
||||||
|
unsigned char rxByte;
|
||||||
|
|
||||||
|
spi_lock ();
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x1f); /* read reg 0x1f */
|
||||||
|
|
||||||
|
bank = spi_read () & 0x3;
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (regNo);
|
||||||
|
rxByte = spi_read ();
|
||||||
|
|
||||||
|
/* check if MAC or MII register */
|
||||||
|
if (((bank == 2) && (regNo <= 0x1a)) ||
|
||||||
|
((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
|
||||||
|
/* ignore first byte and read another byte */
|
||||||
|
rxByte = spi_read ();
|
||||||
|
}
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
spi_unlock ();
|
||||||
|
|
||||||
|
return rxByte;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encReadBuff (unsigned short length, unsigned char *pBuff)
|
||||||
|
{
|
||||||
|
spi_lock ();
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x20 | 0x1a); /* read buffer memory */
|
||||||
|
|
||||||
|
while (length--) {
|
||||||
|
if (pBuff != NULL)
|
||||||
|
*pBuff++ = spi_read ();
|
||||||
|
else
|
||||||
|
spi_write (0);
|
||||||
|
}
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
spi_unlock ();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encWriteBuff (unsigned short length, unsigned char *pBuff)
|
||||||
|
{
|
||||||
|
spi_lock ();
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x60 | 0x1a); /* write buffer memory */
|
||||||
|
|
||||||
|
spi_write (0x00); /* control byte */
|
||||||
|
|
||||||
|
while (length--)
|
||||||
|
spi_write (*pBuff++);
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
spi_unlock ();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encBitSet (unsigned char regNo, unsigned char data)
|
||||||
|
{
|
||||||
|
spi_lock ();
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0x80 | regNo); /* bit field set */
|
||||||
|
spi_write (data);
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
spi_unlock ();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encBitClr (unsigned char regNo, unsigned char data)
|
||||||
|
{
|
||||||
|
spi_lock ();
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0xA0 | regNo); /* bit field clear */
|
||||||
|
spi_write (data);
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
spi_unlock ();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encReset (void)
|
||||||
|
{
|
||||||
|
spi_lock ();
|
||||||
|
enc_cfg_spi ();
|
||||||
|
enc_enable ();
|
||||||
|
|
||||||
|
spi_write (0xff); /* soft reset */
|
||||||
|
|
||||||
|
enc_disable ();
|
||||||
|
spi_unlock ();
|
||||||
|
|
||||||
|
/* sleep 1 ms. See errata pt. 2 */
|
||||||
|
udelay (1000);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void encInit (unsigned char *pEthAddr)
|
||||||
|
{
|
||||||
|
unsigned short phid1 = 0;
|
||||||
|
unsigned short phid2 = 0;
|
||||||
|
|
||||||
|
/* switch to bank 0 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup the buffer space. The reset values are valid for the
|
||||||
|
* other pointers.
|
||||||
|
*/
|
||||||
|
/* We shall not write to ERXST, see errata pt. 5. Instead we
|
||||||
|
have to make sure that ENC_RX_BUS_START is 0. */
|
||||||
|
m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||||
|
m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
|
||||||
|
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
|
||||||
|
m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
|
||||||
|
|
||||||
|
m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||||
|
m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
|
||||||
|
|
||||||
|
next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
|
||||||
|
next_pointer_msb = (ENC_RX_BUF_START >> 8);
|
||||||
|
|
||||||
|
/* verify identification */
|
||||||
|
phid1 = phyRead (PHY_REG_PHID1);
|
||||||
|
phid2 = phyRead (PHY_REG_PHID2);
|
||||||
|
|
||||||
|
if (phid1 != ENC_PHID1_VALUE
|
||||||
|
|| (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
|
||||||
|
printf ("ERROR: failed to identify controller\n");
|
||||||
|
printf ("phid1 = %x, phid2 = %x\n",
|
||||||
|
phid1, (phid2 & ENC_PHID2_MASK));
|
||||||
|
printf ("should be phid1 = %x, phid2 = %x\n",
|
||||||
|
ENC_PHID1_VALUE, ENC_PHID2_VALUE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* --- MAC Initialization ---
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Pull MAC out of Reset */
|
||||||
|
|
||||||
|
/* switch to bank 2 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
|
||||||
|
/* enable MAC to receive frames */
|
||||||
|
/* added some bits from the Linux driver */
|
||||||
|
m_nic_write_retry (CTL_REG_MACON1
|
||||||
|
,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS)
|
||||||
|
,10);
|
||||||
|
|
||||||
|
/* configure pad, tx-crc and duplex */
|
||||||
|
/* added a bit from the Linux driver */
|
||||||
|
m_nic_write_retry (CTL_REG_MACON3
|
||||||
|
,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN)
|
||||||
|
,10);
|
||||||
|
|
||||||
|
/* added 4 new lines from the Linux driver */
|
||||||
|
/* Allow infinite deferals if the medium is continously busy */
|
||||||
|
m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
|
||||||
|
|
||||||
|
/* Late collisions occur beyond 63 bytes */
|
||||||
|
m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
|
||||||
|
|
||||||
|
/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
|
||||||
|
m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
|
||||||
|
* 0x0c for half-duplex. Nothing for full-duplex
|
||||||
|
*/
|
||||||
|
m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
|
||||||
|
|
||||||
|
/* set maximum frame length */
|
||||||
|
m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
|
||||||
|
m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
|
||||||
|
* and 0x15 for full duplex.
|
||||||
|
*/
|
||||||
|
m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
|
||||||
|
|
||||||
|
/* set MAC address */
|
||||||
|
|
||||||
|
/* switch to bank 3 */
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
|
||||||
|
|
||||||
|
m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
|
||||||
|
m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
|
||||||
|
m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
|
||||||
|
m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
|
||||||
|
m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
|
||||||
|
m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PHY Initialization taken from the Linux driver
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Prevent automatic loopback of data beeing transmitted by setting
|
||||||
|
ENC_PHCON2_HDLDIS */
|
||||||
|
phyWrite(PHY_REG_PHCON2, (1<<8));
|
||||||
|
|
||||||
|
/* LEDs configuration
|
||||||
|
* LEDA: LACFG = 0100 -> display link status
|
||||||
|
* LEDB: LBCFG = 0111 -> display TX & RX activity
|
||||||
|
* STRCH = 1 -> LED pulses
|
||||||
|
*/
|
||||||
|
phyWrite(PHY_REG_PHLCON, 0x0472);
|
||||||
|
|
||||||
|
/* Reset PDPXMD-bit => half duplex */
|
||||||
|
phyWrite(PHY_REG_PHCON1, 0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive settings
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ
|
||||||
|
/* enable interrupts */
|
||||||
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
|
||||||
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
|
||||||
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
|
||||||
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
|
||||||
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Read PHY registers.
|
||||||
|
*
|
||||||
|
* NOTE! This function will change to Bank 2.
|
||||||
|
*
|
||||||
|
* Params:
|
||||||
|
* [in] addr address of the register to read
|
||||||
|
*
|
||||||
|
* Returns:
|
||||||
|
* The value in the register
|
||||||
|
*/
|
||||||
|
static unsigned short phyRead (unsigned char addr)
|
||||||
|
{
|
||||||
|
unsigned short ret = 0;
|
||||||
|
|
||||||
|
/* move to bank 2 */
|
||||||
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
|
||||||
|
/* write address to MIREGADR */
|
||||||
|
m_nic_write (CTL_REG_MIREGADR, addr);
|
||||||
|
|
||||||
|
/* set MICMD.MIIRD */
|
||||||
|
m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
|
||||||
|
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
/* move to bank 3 */
|
||||||
|
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
|
||||||
|
/* poll MISTAT.BUSY bit until operation is complete */
|
||||||
|
while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
||||||
|
static int cnt = 0;
|
||||||
|
|
||||||
|
if (cnt++ >= 1000) {
|
||||||
|
/* GJ - this seems extremely dangerous! */
|
||||||
|
/* printf("#"); */
|
||||||
|
cnt = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* taken from the Linux driver */
|
||||||
|
/* move to bank 2 */
|
||||||
|
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
|
||||||
|
/* clear MICMD.MIIRD */
|
||||||
|
m_nic_write (CTL_REG_MICMD, 0);
|
||||||
|
|
||||||
|
ret = (m_nic_read (CTL_REG_MIRDH) << 8);
|
||||||
|
ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
*
|
||||||
|
* Taken from the Linux driver.
|
||||||
|
* Description:
|
||||||
|
* Write PHY registers.
|
||||||
|
*
|
||||||
|
* NOTE! This function will change to Bank 3.
|
||||||
|
*
|
||||||
|
* Params:
|
||||||
|
* [in] addr address of the register to write to
|
||||||
|
* [in] data to be written
|
||||||
|
*
|
||||||
|
* Returns:
|
||||||
|
* None
|
||||||
|
*/
|
||||||
|
static void phyWrite(unsigned char addr, unsigned short data)
|
||||||
|
{
|
||||||
|
/* move to bank 2 */
|
||||||
|
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
|
||||||
|
/* write address to MIREGADR */
|
||||||
|
m_nic_write(CTL_REG_MIREGADR, addr);
|
||||||
|
|
||||||
|
m_nic_write(CTL_REG_MIWRL, data & 0xff);
|
||||||
|
m_nic_write(CTL_REG_MIWRH, data >> 8);
|
||||||
|
|
||||||
|
/* move to bank 3 */
|
||||||
|
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||||
|
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||||
|
|
||||||
|
/* poll MISTAT.BUSY bit until operation is complete */
|
||||||
|
while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
||||||
|
static int cnt = 0;
|
||||||
|
|
||||||
|
if(cnt++ >= 1000) {
|
||||||
|
cnt = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -249,6 +249,13 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
|
||||||
|
|
||||||
mpc5xxx_fec_init_phy(dev, bis);
|
mpc5xxx_fec_init_phy(dev, bis);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Call board-specific PHY fixups (if any)
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_RESET_PHY_R
|
||||||
|
reset_phy();
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Initialize RxBD/TxBD rings
|
* Initialize RxBD/TxBD rings
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -654,6 +654,28 @@ again:
|
||||||
return length;
|
return length;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int smc_write_hwaddr(struct eth_device *dev)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
swap_to(ETHERNET);
|
||||||
|
SMC_SELECT_BANK (dev, 1);
|
||||||
|
#ifdef USE_32_BIT
|
||||||
|
for (i = 0; i < 6; i += 2) {
|
||||||
|
word address;
|
||||||
|
|
||||||
|
address = dev->enetaddr[i + 1] << 8;
|
||||||
|
address |= dev->enetaddr[i];
|
||||||
|
SMC_outw(dev, address, (ADDR0_REG + i));
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
for (i = 0; i < 6; i++)
|
||||||
|
SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
|
||||||
|
#endif
|
||||||
|
swap_to(FLASH);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Open and Initialize the board
|
* Open and Initialize the board
|
||||||
*
|
*
|
||||||
|
@ -662,8 +684,6 @@ again:
|
||||||
*/
|
*/
|
||||||
static int smc_init(struct eth_device *dev, bd_t *bd)
|
static int smc_init(struct eth_device *dev, bd_t *bd)
|
||||||
{
|
{
|
||||||
int i;
|
|
||||||
|
|
||||||
swap_to(ETHERNET);
|
swap_to(ETHERNET);
|
||||||
|
|
||||||
PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
|
PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
|
||||||
|
@ -680,20 +700,6 @@ static int smc_init(struct eth_device *dev, bd_t *bd)
|
||||||
/* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
|
/* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
|
||||||
/* SMC_SELECT_BANK(dev, 0); */
|
/* SMC_SELECT_BANK(dev, 0); */
|
||||||
/* SMC_outw(dev, 0, RPC_REG); */
|
/* SMC_outw(dev, 0, RPC_REG); */
|
||||||
SMC_SELECT_BANK (dev, 1);
|
|
||||||
|
|
||||||
#ifdef USE_32_BIT
|
|
||||||
for (i = 0; i < 6; i += 2) {
|
|
||||||
word address;
|
|
||||||
|
|
||||||
address = dev->enetaddr[i + 1] << 8;
|
|
||||||
address |= dev->enetaddr[i];
|
|
||||||
SMC_outw(dev, address, (ADDR0_REG + i));
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
for (i = 0; i < 6; i++)
|
|
||||||
SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
|
|
||||||
#endif
|
|
||||||
|
|
||||||
printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
|
printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
|
||||||
|
|
||||||
|
@ -1360,6 +1366,7 @@ int smc91111_initialize(u8 dev_num, int base_addr)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
memset(dev, 0, sizeof(*dev));
|
||||||
priv->dev_num = dev_num;
|
priv->dev_num = dev_num;
|
||||||
dev->priv = priv;
|
dev->priv = priv;
|
||||||
dev->iobase = base_addr;
|
dev->iobase = base_addr;
|
||||||
|
@ -1374,6 +1381,7 @@ int smc91111_initialize(u8 dev_num, int base_addr)
|
||||||
dev->halt = smc_halt;
|
dev->halt = smc_halt;
|
||||||
dev->send = smc_send;
|
dev->send = smc_send;
|
||||||
dev->recv = smc_rcv;
|
dev->recv = smc_rcv;
|
||||||
|
dev->write_hwaddr = smc_write_hwaddr;
|
||||||
sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
|
sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
|
||||||
|
|
||||||
eth_register(dev);
|
eth_register(dev);
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <net.h>
|
#include <net.h>
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
|
#include <malloc.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
|
||||||
#undef DEBUG
|
#undef DEBUG
|
||||||
|
@ -63,26 +64,19 @@
|
||||||
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
|
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
unsigned int baseaddress; /* Base address for device (IPIF) */
|
u32 baseaddress; /* Base address for device (IPIF) */
|
||||||
unsigned int nexttxbuffertouse; /* Next TX buffer to write to */
|
u32 nexttxbuffertouse; /* Next TX buffer to write to */
|
||||||
unsigned int nextrxbuffertouse; /* Next RX buffer to read from */
|
u32 nextrxbuffertouse; /* Next RX buffer to read from */
|
||||||
unsigned char deviceid; /* Unique ID of device - for future */
|
uchar deviceid; /* Unique ID of device - for future */
|
||||||
} xemaclite;
|
} xemaclite;
|
||||||
|
|
||||||
static xemaclite emaclite;
|
static xemaclite emaclite;
|
||||||
|
|
||||||
static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
|
static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
|
||||||
|
|
||||||
/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
|
static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount)
|
||||||
#ifdef CONFIG_ENV_IS_NOWHERE
|
|
||||||
static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
|
|
||||||
#else
|
|
||||||
static u8 emacaddr[ENET_ADDR_LENGTH];
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
|
|
||||||
{
|
{
|
||||||
unsigned int i;
|
u32 i;
|
||||||
u32 alignbuffer;
|
u32 alignbuffer;
|
||||||
u32 *to32ptr;
|
u32 *to32ptr;
|
||||||
u32 *from32ptr;
|
u32 *from32ptr;
|
||||||
|
@ -107,9 +101,9 @@ void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
|
static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount)
|
||||||
{
|
{
|
||||||
unsigned i;
|
u32 i;
|
||||||
u32 alignbuffer;
|
u32 alignbuffer;
|
||||||
u32 *to32ptr = (u32 *) destptr;
|
u32 *to32ptr = (u32 *) destptr;
|
||||||
u32 *from32ptr;
|
u32 *from32ptr;
|
||||||
|
@ -134,23 +128,16 @@ void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
|
||||||
*to32ptr++ = alignbuffer;
|
*to32ptr++ = alignbuffer;
|
||||||
}
|
}
|
||||||
|
|
||||||
void eth_halt (void)
|
static void emaclite_halt(struct eth_device *dev)
|
||||||
{
|
{
|
||||||
debug ("eth_halt\n");
|
debug ("eth_halt\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
int eth_init (bd_t * bis)
|
static int emaclite_init(struct eth_device *dev, bd_t *bis)
|
||||||
{
|
{
|
||||||
uchar enetaddr[6];
|
|
||||||
|
|
||||||
debug ("EmacLite Initialization Started\n");
|
debug ("EmacLite Initialization Started\n");
|
||||||
memset (&emaclite, 0, sizeof (xemaclite));
|
memset (&emaclite, 0, sizeof (xemaclite));
|
||||||
emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
|
emaclite.baseaddress = dev->iobase;
|
||||||
|
|
||||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
|
|
||||||
memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH);
|
|
||||||
eth_setenv_enetaddr("ethaddr", enetaddr);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TX - TX_PING & TX_PONG initialization
|
* TX - TX_PING & TX_PONG initialization
|
||||||
|
@ -158,7 +145,7 @@ int eth_init (bd_t * bis)
|
||||||
/* Restart PING TX */
|
/* Restart PING TX */
|
||||||
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
|
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
|
||||||
/* Copy MAC address */
|
/* Copy MAC address */
|
||||||
xemaclite_alignedwrite (enetaddr,
|
xemaclite_alignedwrite (dev->enetaddr,
|
||||||
emaclite.baseaddress, ENET_ADDR_LENGTH);
|
emaclite.baseaddress, ENET_ADDR_LENGTH);
|
||||||
/* Set the length */
|
/* Set the length */
|
||||||
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
|
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
|
||||||
|
@ -171,7 +158,7 @@ int eth_init (bd_t * bis)
|
||||||
#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
|
#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
|
||||||
/* The same operation with PONG TX */
|
/* The same operation with PONG TX */
|
||||||
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
|
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
|
||||||
xemaclite_alignedwrite (enetaddr, emaclite.baseaddress +
|
xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress +
|
||||||
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
|
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
|
||||||
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
|
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
|
||||||
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
|
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
|
||||||
|
@ -194,7 +181,7 @@ int eth_init (bd_t * bis)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int xemaclite_txbufferavailable (xemaclite * instanceptr)
|
static int xemaclite_txbufferavailable (xemaclite *instanceptr)
|
||||||
{
|
{
|
||||||
u32 reg;
|
u32 reg;
|
||||||
u32 txpingbusy;
|
u32 txpingbusy;
|
||||||
|
@ -216,12 +203,12 @@ int xemaclite_txbufferavailable (xemaclite * instanceptr)
|
||||||
return (!(txpingbusy && txpongbusy));
|
return (!(txpingbusy && txpongbusy));
|
||||||
}
|
}
|
||||||
|
|
||||||
int eth_send (volatile void *ptr, int len) {
|
static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
|
||||||
|
{
|
||||||
|
u32 reg;
|
||||||
|
u32 baseaddress;
|
||||||
|
|
||||||
unsigned int reg;
|
u32 maxtry = 1000;
|
||||||
unsigned int baseaddress;
|
|
||||||
|
|
||||||
unsigned maxtry = 1000;
|
|
||||||
|
|
||||||
if (len > ENET_MAX_MTU)
|
if (len > ENET_MAX_MTU)
|
||||||
len = ENET_MAX_MTU;
|
len = ENET_MAX_MTU;
|
||||||
|
@ -293,11 +280,11 @@ int eth_send (volatile void *ptr, int len) {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int eth_rx (void)
|
static int emaclite_recv(struct eth_device *dev)
|
||||||
{
|
{
|
||||||
unsigned int length;
|
u32 length;
|
||||||
unsigned int reg;
|
u32 reg;
|
||||||
unsigned int baseaddress;
|
u32 baseaddress;
|
||||||
|
|
||||||
baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
|
baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
|
||||||
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
|
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
|
||||||
|
@ -322,7 +309,7 @@ int eth_rx (void)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
/* Get the length of the frame that arrived */
|
/* Get the length of the frame that arrived */
|
||||||
switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
|
switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
|
||||||
0xFFFF0000 ) >> 16) {
|
0xFFFF0000 ) >> 16) {
|
||||||
case 0x806:
|
case 0x806:
|
||||||
length = 42 + 20; /* FIXME size of ARP */
|
length = 42 + 20; /* FIXME size of ARP */
|
||||||
|
@ -330,7 +317,7 @@ int eth_rx (void)
|
||||||
break;
|
break;
|
||||||
case 0x800:
|
case 0x800:
|
||||||
length = 14 + 14 +
|
length = 14 + 14 +
|
||||||
(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
|
(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10))) &
|
||||||
0xFFFF0000) >> 16); /* FIXME size of IP packet */
|
0xFFFF0000) >> 16); /* FIXME size of IP packet */
|
||||||
debug ("IP Packet\n");
|
debug ("IP Packet\n");
|
||||||
break;
|
break;
|
||||||
|
@ -353,3 +340,26 @@ int eth_rx (void)
|
||||||
return 1;
|
return 1;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
|
||||||
|
{
|
||||||
|
struct eth_device *dev;
|
||||||
|
|
||||||
|
dev = malloc(sizeof(*dev));
|
||||||
|
if (dev == NULL)
|
||||||
|
hang();
|
||||||
|
|
||||||
|
memset(dev, 0, sizeof(*dev));
|
||||||
|
sprintf(dev->name, "Xilinx_Emaclite");
|
||||||
|
|
||||||
|
dev->iobase = base_addr;
|
||||||
|
dev->priv = 0;
|
||||||
|
dev->init = emaclite_init;
|
||||||
|
dev->halt = emaclite_halt;
|
||||||
|
dev->send = emaclite_send;
|
||||||
|
dev->recv = emaclite_recv;
|
||||||
|
|
||||||
|
eth_register(dev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
|
@ -1223,8 +1223,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
|
||||||
i = 50;
|
i = 50;
|
||||||
do {
|
do {
|
||||||
err = curphy->read_status(uec->mii_info);
|
err = curphy->read_status(uec->mii_info);
|
||||||
|
if (!(((i-- > 0) && !uec->mii_info->link) || err))
|
||||||
|
break;
|
||||||
udelay(100000);
|
udelay(100000);
|
||||||
} while (((i-- > 0) && !uec->mii_info->link) || err);
|
} while (1);
|
||||||
|
|
||||||
if (err || i <= 0)
|
if (err || i <= 0)
|
||||||
printf("warning: %s: timeout on PHY link\n", dev->name);
|
printf("warning: %s: timeout on PHY link\n", dev->name);
|
||||||
|
|
|
@ -351,6 +351,15 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info)
|
||||||
static int genmii_config_aneg (struct uec_mii_info *mii_info)
|
static int genmii_config_aneg (struct uec_mii_info *mii_info)
|
||||||
{
|
{
|
||||||
if (mii_info->autoneg) {
|
if (mii_info->autoneg) {
|
||||||
|
/* Speed up the common case, if link is already up, speed and
|
||||||
|
duplex match, skip auto neg as it already matches */
|
||||||
|
if (!genmii_read_status(mii_info) && mii_info->link)
|
||||||
|
if (mii_info->duplex == DUPLEX_FULL &&
|
||||||
|
mii_info->speed == SPEED_100)
|
||||||
|
if (mii_info->advertising &
|
||||||
|
ADVERTISED_100baseT_Full)
|
||||||
|
return 0;
|
||||||
|
|
||||||
config_genmii_advert (mii_info);
|
config_genmii_advert (mii_info);
|
||||||
genmii_restart_aneg (mii_info);
|
genmii_restart_aneg (mii_info);
|
||||||
} else
|
} else
|
||||||
|
@ -389,7 +398,6 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
|
||||||
status = phy_read(mii_info, PHY_BMSR);
|
status = phy_read(mii_info, PHY_BMSR);
|
||||||
}
|
}
|
||||||
mii_info->link = 1;
|
mii_info->link = 1;
|
||||||
udelay(500000); /* another 500 ms (results in faster booting) */
|
|
||||||
} else {
|
} else {
|
||||||
if (status & PHY_BMSR_LS)
|
if (status & PHY_BMSR_LS)
|
||||||
mii_info->link = 1;
|
mii_info->link = 1;
|
||||||
|
|
|
@ -70,6 +70,7 @@
|
||||||
#define CONFIG_CMD_PORTIO /* Port I/O */
|
#define CONFIG_CMD_PORTIO /* Port I/O */
|
||||||
#define CONFIG_CMD_REGINFO /* Register dump */
|
#define CONFIG_CMD_REGINFO /* Register dump */
|
||||||
#define CONFIG_CMD_REISER /* Reiserfs support */
|
#define CONFIG_CMD_REISER /* Reiserfs support */
|
||||||
|
#define CONFIG_CMD_RARP /* rarpboot support */
|
||||||
#define CONFIG_CMD_RUN /* run command in env variable */
|
#define CONFIG_CMD_RUN /* run command in env variable */
|
||||||
#define CONFIG_CMD_SAVEENV /* saveenv */
|
#define CONFIG_CMD_SAVEENV /* saveenv */
|
||||||
#define CONFIG_CMD_SAVES /* save S record dump */
|
#define CONFIG_CMD_SAVES /* save S record dump */
|
||||||
|
|
|
@ -198,6 +198,6 @@
|
||||||
#define CONFIG_INITRD_TAG
|
#define CONFIG_INITRD_TAG
|
||||||
#define CONFIG_MMC 1
|
#define CONFIG_MMC 1
|
||||||
/* we use this ethernet chip */
|
/* we use this ethernet chip */
|
||||||
#define CONFIG_ENC28J60
|
#define CONFIG_ENC28J60_LPC2292
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|
|
@ -156,6 +156,6 @@
|
||||||
#define CONFIG_INITRD_TAG
|
#define CONFIG_INITRD_TAG
|
||||||
#define CONFIG_MMC 1
|
#define CONFIG_MMC 1
|
||||||
/* we use this ethernet chip */
|
/* we use this ethernet chip */
|
||||||
#define CONFIG_ENC28J60
|
#define CONFIG_ENC28J60_LPC2292
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|
|
@ -54,6 +54,8 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
|
||||||
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
|
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
|
||||||
int e1000_initialize(bd_t *bis);
|
int e1000_initialize(bd_t *bis);
|
||||||
int eepro100_initialize(bd_t *bis);
|
int eepro100_initialize(bd_t *bis);
|
||||||
|
int enc28j60_initialize(unsigned int bus, unsigned int cs,
|
||||||
|
unsigned int max_hz, unsigned int mode);
|
||||||
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
|
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
|
||||||
int ethoc_initialize(u8 dev_num, int base_addr);
|
int ethoc_initialize(u8 dev_num, int base_addr);
|
||||||
int eth_3com_initialize (bd_t * bis);
|
int eth_3com_initialize (bd_t * bis);
|
||||||
|
@ -85,9 +87,9 @@ int skge_initialize(bd_t *bis);
|
||||||
int smc911x_initialize(u8 dev_num, int base_addr);
|
int smc911x_initialize(u8 dev_num, int base_addr);
|
||||||
int smc91111_initialize(u8 dev_num, int base_addr);
|
int smc91111_initialize(u8 dev_num, int base_addr);
|
||||||
int tsi108_eth_initialize(bd_t *bis);
|
int tsi108_eth_initialize(bd_t *bis);
|
||||||
int uec_initialize(int index);
|
|
||||||
int uec_standard_init(bd_t *bis);
|
int uec_standard_init(bd_t *bis);
|
||||||
int uli526x_initialize(bd_t *bis);
|
int uli526x_initialize(bd_t *bis);
|
||||||
|
int xilinx_emaclite_initialize (bd_t *bis, int base_addr);
|
||||||
int sh_eth_initialize(bd_t *bis);
|
int sh_eth_initialize(bd_t *bis);
|
||||||
int dm9000_initialize(bd_t *bis);
|
int dm9000_initialize(bd_t *bis);
|
||||||
|
|
||||||
|
|
|
@ -32,7 +32,7 @@ COBJS-$(CONFIG_CMD_DNS) += dns.o
|
||||||
COBJS-$(CONFIG_CMD_NET) += eth.o
|
COBJS-$(CONFIG_CMD_NET) += eth.o
|
||||||
COBJS-$(CONFIG_CMD_NET) += net.o
|
COBJS-$(CONFIG_CMD_NET) += net.o
|
||||||
COBJS-$(CONFIG_CMD_NFS) += nfs.o
|
COBJS-$(CONFIG_CMD_NFS) += nfs.o
|
||||||
COBJS-$(CONFIG_CMD_NET) += rarp.o
|
COBJS-$(CONFIG_CMD_RARP) += rarp.o
|
||||||
COBJS-$(CONFIG_CMD_SNTP) += sntp.o
|
COBJS-$(CONFIG_CMD_SNTP) += sntp.o
|
||||||
COBJS-$(CONFIG_CMD_NET) += tftp.o
|
COBJS-$(CONFIG_CMD_NET) += tftp.o
|
||||||
|
|
||||||
|
|
16
net/eth.c
16
net/eth.c
|
@ -263,7 +263,6 @@ int eth_initialize(bd_t *bis)
|
||||||
dev = dev->next;
|
dev = dev->next;
|
||||||
} while(dev != eth_devices);
|
} while(dev != eth_devices);
|
||||||
|
|
||||||
#ifdef CONFIG_NET_MULTI
|
|
||||||
/* update current ethernet name */
|
/* update current ethernet name */
|
||||||
if (eth_current) {
|
if (eth_current) {
|
||||||
char *act = getenv("ethact");
|
char *act = getenv("ethact");
|
||||||
|
@ -271,7 +270,6 @@ int eth_initialize(bd_t *bis)
|
||||||
setenv("ethact", eth_current->name);
|
setenv("ethact", eth_current->name);
|
||||||
} else
|
} else
|
||||||
setenv("ethact", NULL);
|
setenv("ethact", NULL);
|
||||||
#endif
|
|
||||||
|
|
||||||
putc ('\n');
|
putc ('\n');
|
||||||
}
|
}
|
||||||
|
@ -441,7 +439,7 @@ int eth_receive(volatile void *packet, int length)
|
||||||
void eth_try_another(int first_restart)
|
void eth_try_another(int first_restart)
|
||||||
{
|
{
|
||||||
static struct eth_device *first_failed = NULL;
|
static struct eth_device *first_failed = NULL;
|
||||||
char *ethrotate;
|
char *ethrotate, *act;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Do not rotate between network interfaces when
|
* Do not rotate between network interfaces when
|
||||||
|
@ -460,21 +458,16 @@ void eth_try_another(int first_restart)
|
||||||
|
|
||||||
eth_current = eth_current->next;
|
eth_current = eth_current->next;
|
||||||
|
|
||||||
#ifdef CONFIG_NET_MULTI
|
|
||||||
/* update current ethernet name */
|
/* update current ethernet name */
|
||||||
{
|
act = getenv("ethact");
|
||||||
char *act = getenv("ethact");
|
if (act == NULL || strcmp(act, eth_current->name) != 0)
|
||||||
if (act == NULL || strcmp(act, eth_current->name) != 0)
|
setenv("ethact", eth_current->name);
|
||||||
setenv("ethact", eth_current->name);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (first_failed == eth_current) {
|
if (first_failed == eth_current) {
|
||||||
NetRestartWrap = 1;
|
NetRestartWrap = 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_NET_MULTI
|
|
||||||
void eth_set_current(void)
|
void eth_set_current(void)
|
||||||
{
|
{
|
||||||
static char *act = NULL;
|
static char *act = NULL;
|
||||||
|
@ -501,7 +494,6 @@ void eth_set_current(void)
|
||||||
|
|
||||||
setenv("ethact", eth_current->name);
|
setenv("ethact", eth_current->name);
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
char *eth_get_name (void)
|
char *eth_get_name (void)
|
||||||
{
|
{
|
||||||
|
|
11
net/net.c
11
net/net.c
|
@ -80,7 +80,9 @@
|
||||||
#include <net.h>
|
#include <net.h>
|
||||||
#include "bootp.h"
|
#include "bootp.h"
|
||||||
#include "tftp.h"
|
#include "tftp.h"
|
||||||
|
#ifdef CONFIG_CMD_RARP
|
||||||
#include "rarp.h"
|
#include "rarp.h"
|
||||||
|
#endif
|
||||||
#include "nfs.h"
|
#include "nfs.h"
|
||||||
#ifdef CONFIG_STATUS_LED
|
#ifdef CONFIG_STATUS_LED
|
||||||
#include <status_led.h>
|
#include <status_led.h>
|
||||||
|
@ -401,11 +403,13 @@ restart:
|
||||||
BootpRequest ();
|
BootpRequest ();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_RARP)
|
||||||
case RARP:
|
case RARP:
|
||||||
RarpTry = 0;
|
RarpTry = 0;
|
||||||
NetOurIP = 0;
|
NetOurIP = 0;
|
||||||
RarpRequest ();
|
RarpRequest ();
|
||||||
break;
|
break;
|
||||||
|
#endif
|
||||||
#if defined(CONFIG_CMD_PING)
|
#if defined(CONFIG_CMD_PING)
|
||||||
case PING:
|
case PING:
|
||||||
PingStart();
|
PingStart();
|
||||||
|
@ -1492,6 +1496,7 @@ NetReceive(volatile uchar * inpkt, int len)
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
#ifdef CONFIG_CMD_RARP
|
||||||
case PROT_RARP:
|
case PROT_RARP:
|
||||||
debug("Got RARP\n");
|
debug("Got RARP\n");
|
||||||
arp = (ARP_t *)ip;
|
arp = (ARP_t *)ip;
|
||||||
|
@ -1515,7 +1520,7 @@ NetReceive(volatile uchar * inpkt, int len)
|
||||||
(*packetHandler)(0,0,0,0);
|
(*packetHandler)(0,0,0,0);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
#endif
|
||||||
case PROT_IP:
|
case PROT_IP:
|
||||||
debug("Got IP\n");
|
debug("Got IP\n");
|
||||||
/* Before we start poking the header, make sure it is there */
|
/* Before we start poking the header, make sure it is there */
|
||||||
|
@ -1729,10 +1734,12 @@ static int net_check_prereq (proto_t protocol)
|
||||||
}
|
}
|
||||||
/* Fall through */
|
/* Fall through */
|
||||||
|
|
||||||
case DHCP:
|
#ifdef CONFIG_CMD_RARP
|
||||||
case RARP:
|
case RARP:
|
||||||
|
#endif
|
||||||
case BOOTP:
|
case BOOTP:
|
||||||
case CDP:
|
case CDP:
|
||||||
|
case DHCP:
|
||||||
if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) {
|
if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) {
|
||||||
#ifdef CONFIG_NET_MULTI
|
#ifdef CONFIG_NET_MULTI
|
||||||
extern int eth_get_dev_index (void);
|
extern int eth_get_dev_index (void);
|
||||||
|
|
Loading…
Add table
Reference in a new issue