rockchip: rk322x: add basic soc support

Enable soc support for SPL and U-boot skeleton.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang 2017-06-23 17:17:52 +08:00 committed by Philipp Tomsich
parent b647442ce8
commit 168eef7ada
10 changed files with 404 additions and 0 deletions

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@ -19,6 +19,7 @@ enum {
ROCKCHIP_SYSCON_PMUGRF, ROCKCHIP_SYSCON_PMUGRF,
ROCKCHIP_SYSCON_PMUSGRF, ROCKCHIP_SYSCON_PMUSGRF,
ROCKCHIP_SYSCON_CIC, ROCKCHIP_SYSCON_CIC,
ROCKCHIP_SYSCON_MSCH,
}; };
/* Standard Rockchip clock numbers */ /* Standard Rockchip clock numbers */

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@ -28,6 +28,19 @@ config ROCKCHIP_RK3188
Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
UART, SPI, I2C and PWMs. UART, SPI, I2C and PWMs.
config ROCKCHIP_RK322X
bool "Support Rockchip RK3228/RK3229"
select CPU_V7
select SUPPORT_SPL
select SPL
select ROCKCHIP_BROM_HELPER
select DEBUG_UART_BOARD_INIT
help
The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
config ROCKCHIP_RK3288 config ROCKCHIP_RK3288
bool "Support Rockchip RK3288" bool "Support Rockchip RK3288"
select CPU_V7 select CPU_V7

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@ -12,11 +12,13 @@ obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
else ifdef CONFIG_SPL_BUILD else ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
else else
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
ifdef CONFIG_RAM ifdef CONFIG_RAM
@ -32,6 +34,7 @@ ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif endif
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/

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@ -0,0 +1,77 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
#include <asm/arch/cru_rk322x.h>
#include <asm/arch/grf_rk322x.h>
#include <asm/arch/hardware.h>
#include <asm/arch/timer.h>
#include <asm/arch/uart.h>
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0x11000000
#define SGRF_BASE 0x10140000
#define DEBUG_UART_BASE 0x11030000
void board_debug_uart_init(void)
{
static struct rk322x_grf * const grf = (void *)GRF_BASE;
/* Enable early UART2 channel 1 on the RK322x */
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B2_MASK,
GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
/* Set channel C as UART2 input */
rk_clrsetreg(&grf->con_iomux,
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("SPL Init");
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
rockchip_timer_init();
printf("timer init done\n");
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
#endif
}

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@ -0,0 +1,136 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/grf_rk322x.h>
#include <asm/arch/boot_mode.h>
DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0x11000000
static void setup_boot_mode(void)
{
struct rk322x_grf *const grf = (void *)GRF_BASE;
int boot_mode = readl(&grf->os_reg[4]);
debug("boot mode %x.\n", boot_mode);
/* Clear boot mode */
writel(BOOT_NORMAL, &grf->os_reg[4]);
switch (boot_mode) {
case BOOT_FASTBOOT:
printf("enter fastboot!\n");
setenv("preboot", "setenv preboot; fastboot usb0");
break;
case BOOT_UMS:
printf("enter UMS!\n");
setenv("preboot", "setenv preboot; ums mmc 0");
break;
}
}
__weak int rk_board_late_init(void)
{
return 0;
}
int board_late_init(void)
{
setup_boot_mode();
return rk_board_late_init();
}
int board_init(void)
{
#include <asm/arch/grf_rk322x.h>
/* Enable early UART2 channel 1 on the RK322x */
#define GRF_BASE 0x11000000
struct rk322x_grf * const grf = (void *)GRF_BASE;
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B2_MASK,
GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
/* Set channel C as UART2 input */
rk_clrsetreg(&grf->con_iomux,
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
return 0;
}
int dram_init_banksize(void)
{
/* Reserve 0x200000 for OPTEE */
gd->bd->bi_dram[0].start = 0x60000000;
gd->bd->bi_dram[0].size = 0x8400000;
gd->bd->bi_dram[1].start = 0x6a400000;
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].start;
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif
#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
#include <usb.h>
#include <usb/dwc2_udc.h>
static struct dwc2_plat_otg_data rk322x_otg_data = {
.rx_fifo_sz = 512,
.np_tx_fifo_sz = 16,
.tx_fifo_sz = 128,
};
int board_usb_init(int index, enum usb_init_type init)
{
int node;
const char *mode;
bool matched = false;
const void *blob = gd->fdt_blob;
/* find the usb_otg node */
node = fdt_node_offset_by_compatible(blob, -1,
"rockchip,rk3288-usb");
while (node > 0) {
mode = fdt_getprop(blob, node, "dr_mode", NULL);
if (mode && strcmp(mode, "otg") == 0) {
matched = true;
break;
}
node = fdt_node_offset_by_compatible(blob, node,
"rockchip,rk3288-usb");
}
if (!matched) {
debug("Not found usb_otg device\n");
return -ENODEV;
}
rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
return dwc2_udc_probe(&rk322x_otg_data);
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
return 0;
}
#endif

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@ -0,0 +1,18 @@
if ROCKCHIP_RK322X
config TARGET_EVB_RK3229
bool "EVB_RK3229"
select BOARD_LATE_INIT
config SYS_SOC
default "rockchip"
config SYS_MALLOC_F_LEN
default 0x400
config SPL_SERIAL_SUPPORT
default y
source "board/rockchip/evb_rk3229/Kconfig"
endif

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@ -0,0 +1,9 @@
#
# (C) Copyright 2017 Rockchip Electronics Co., Ltd.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clk_rk322x.o
obj-y += syscon_rk322x.o

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@ -0,0 +1,32 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk322x.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk322x_cru), devp);
}
void *rockchip_get_cru(void)
{
struct rk322x_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}

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@ -0,0 +1,22 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
static const struct udevice_id rk322x_syscon_ids[] = {
{ .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF },
{ .compatible = "rockchip,rk3228-msch", .data = ROCKCHIP_SYSCON_MSCH },
{ }
};
U_BOOT_DRIVER(syscon_rk322x) = {
.name = "rk322x_syscon",
.id = UCLASS_SYSCON,
.of_match = rk322x_syscon_ids,
};

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@ -0,0 +1,93 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_RK322X_COMMON_H
#define __CONFIG_RK322X_COMMON_H
#include <asm/arch/hardware.h>
#include "rockchip-common.h"
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10088000
#define CONFIG_SPL_TEXT_BASE 0x10081004
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 2
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE 0x80000000
#ifndef CONFIG_SPL_BUILD
/* usb otg */
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_VBUS_DRAW 0
/* fastboot */
#define CONFIG_CMD_FASTBOOT
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_FASTBOOT_FLASH
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
/* usb mass storage */
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
#define CONFIG_G_DNL_VENDOR_NUM 0x2207
#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
/* usb host */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX
#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x60000000\0" \
"pxefile_addr_r=0x60100000\0" \
"fdt_addr_r=0x61f00000\0" \
"kernel_addr_r=0x62000000\0" \
"ramdisk_addr_r=0x64000000\0"
#include <config_distro_bootcmd.h>
/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
* so limit the fdt reallocation to that */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x7fffffff\0" \
"partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif
#define CONFIG_PREBOOT
#endif