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board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb
This patch enables ethernet support for ls1012a2g5rdb. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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7ab16479e1
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28e3c39e53
2 changed files with 67 additions and 8 deletions
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@ -59,6 +59,36 @@ config SYS_SOC
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config SYS_CONFIG_NAME
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config SYS_CONFIG_NAME
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default "ls1012a2g5rdb"
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default "ls1012a2g5rdb"
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if FSL_PFE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select PHYLIB
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imply CONFIG_PHYLIB_10G
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imply CONFIG_PHY_AQUANTIA
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config SYS_LS_PFE_FW_ADDR
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hex "Flash address of PFE firmware"
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default 0x40a00000
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config DDR_PFE_PHYS_BASEADDR
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hex "PFE DDR physical base address"
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default 0x03800000
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config DDR_PFE_BASEADDR
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hex "PFE DDR base address"
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default 0x83800000
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config PFE_EMAC1_PHY_ADDR
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hex "PFE DDR base address"
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default 0x2
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config PFE_EMAC2_PHY_ADDR
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hex "PFE DDR base address"
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default 0x1
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endif
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source "board/freescale/common/Kconfig"
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source "board/freescale/common/Kconfig"
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endif
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endif
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@ -26,6 +26,7 @@
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static inline void ls1012ardb_reset_phy(void)
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static inline void ls1012ardb_reset_phy(void)
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{
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{
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#ifdef CONFIG_TARGET_LS1012ARDB
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/* Through reset IO expander reset both RGMII and SGMII PHYs */
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/* Through reset IO expander reset both RGMII and SGMII PHYs */
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i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
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@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
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mdelay(10);
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mdelay(10);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
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mdelay(50);
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mdelay(50);
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#endif
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}
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}
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int pfe_eth_board_init(struct udevice *dev)
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int pfe_eth_board_init(struct udevice *dev)
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@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
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struct mii_dev *bus;
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struct mii_dev *bus;
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struct pfe_mdio_info mac_mdio_info;
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struct pfe_mdio_info mac_mdio_info;
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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int srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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if (!init_done) {
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if (!init_done) {
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ls1012ardb_reset_phy();
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ls1012ardb_reset_phy();
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@ -59,14 +66,36 @@ int pfe_eth_board_init(struct udevice *dev)
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pfe_set_mdio(priv->gemac_port,
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pfe_set_mdio(priv->gemac_port,
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miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
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miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
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if (!priv->gemac_port) {
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switch (srds_s1) {
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/* MAC1 */
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case 0x3508:
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pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
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if (!priv->gemac_port) {
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PHY_INTERFACE_MODE_SGMII);
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/* MAC1 */
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} else {
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pfe_set_phy_address_mode(priv->gemac_port,
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/* MAC2 */
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CONFIG_PFE_EMAC1_PHY_ADDR,
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pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII);
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PHY_INTERFACE_MODE_RGMII_TXID);
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} else {
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/* MAC2 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_RGMII_TXID);
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}
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break;
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case 0x2208:
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if (!priv->gemac_port) {
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/* MAC1 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC1_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII_2500);
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} else {
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/* MAC2 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII_2500);
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}
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break;
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default:
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printf("unsupported SerDes PRCTL= %d\n", srds_s1);
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break;
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}
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}
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return 0;
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return 0;
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}
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}
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