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board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb

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This patch enables ethernet support for ls1012a2g5rdb.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Calvin Johnson 2018-03-08 15:30:31 +05:30 • committed by Joe Hershberger
parent 7ab16479e1
commit 28e3c39e53
2 changed files with 67 additions and 8 deletions
board/freescale/ls1012ardb
Kconfigeth.c

30
board/freescale/ls1012ardb/Kconfig
View file

@ -59,6 +59,36 @@ config SYS_SOC
config SYS_CONFIG_NAME config SYS_CONFIG_NAME
default "ls1012a2g5rdb" default "ls1012a2g5rdb"
if FSL_PFE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select PHYLIB
imply CONFIG_PHYLIB_10G
imply CONFIG_PHY_AQUANTIA
config SYS_LS_PFE_FW_ADDR
hex "Flash address of PFE firmware"
default 0x40a00000
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"
default 0x03800000
config DDR_PFE_BASEADDR
hex "PFE DDR base address"
default 0x83800000
config PFE_EMAC1_PHY_ADDR
hex "PFE DDR base address"
default 0x2
config PFE_EMAC2_PHY_ADDR
hex "PFE DDR base address"
default 0x1
endif
source "board/freescale/common/Kconfig" source "board/freescale/common/Kconfig"
endif endif

45
board/freescale/ls1012ardb/eth.c
View file

@ -26,6 +26,7 @@
static inline void ls1012ardb_reset_phy(void) static inline void ls1012ardb_reset_phy(void)
{ {
#ifdef CONFIG_TARGET_LS1012ARDB
/* Through reset IO expander reset both RGMII and SGMII PHYs */ /* Through reset IO expander reset both RGMII and SGMII PHYs */
i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
mdelay(10); mdelay(10);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
mdelay(50); mdelay(50);
#endif
} }
int pfe_eth_board_init(struct udevice *dev) int pfe_eth_board_init(struct udevice *dev)
@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus; struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info; struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev); struct pfe_eth_dev *priv = dev_get_priv(dev);
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
if (!init_done) { if (!init_done) {
ls1012ardb_reset_phy(); ls1012ardb_reset_phy();
@ -59,14 +66,36 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(priv->gemac_port, pfe_set_mdio(priv->gemac_port,
miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
if (!priv->gemac_port) { switch (srds_s1) {
/* MAC1 */ case 0x3508:
pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR, if (!priv->gemac_port) {
PHY_INTERFACE_MODE_SGMII); /* MAC1 */
} else { pfe_set_phy_address_mode(priv->gemac_port,
/* MAC2 */ CONFIG_PFE_EMAC1_PHY_ADDR,
pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
PHY_INTERFACE_MODE_RGMII_TXID); } else {
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
PHY_INTERFACE_MODE_RGMII_TXID);
}
break;
case 0x2208:
if (!priv->gemac_port) {
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC1_PHY_ADDR,
PHY_INTERFACE_MODE_SGMII_2500);
} else {
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
PHY_INTERFACE_MODE_SGMII_2500);
}
break;
default:
printf("unsupported SerDes PRCTL= %d\n", srds_s1);
break;
} }
return 0; return 0;
} }