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ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMX
Use the DDR3 dtsi files generated by STM32CubeMX 5.6.0 Speed Bin Grade = using DDR3-1066G / 8-8-8 and all others parameters at default value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay
parent
f17412ed38
commit
414315bcdf
2 changed files with 46 additions and 50 deletions
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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/*
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* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
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* DDR type: DDR3 / DDR3L
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* DDR width: 16bits
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* DDR density: 4Gb
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* System frequency: 533000Khz
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* Relaxed Timing Mode: false
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* Address mapping type: RBC
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*
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* STM32MP157C DK1/DK2 BOARD configuration
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* 1x DDR3L 4Gb, 16-bit, 533MHz.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 16
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* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
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* DDR density 4
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* timing mode optimized
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* Scheduling/QoS options : type = 2
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* address mapping : RBC
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* Tc > + 85C : N
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* Save Date: 2020.02.20, save Time: 18:45:20
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*/
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#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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#define DDR_MSTR 0x00041401
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#define DDR_MRCTRL0 0x00000010
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@ -51,15 +49,6 @@
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00070707
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x1F000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x06060606
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#define DDR_ADDRMAP6 0x0F060606
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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@ -84,6 +73,15 @@
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_ADDRMAP1 0x00070707
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x1F000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x06060606
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#define DDR_ADDRMAP6 0x0F060606
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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@ -1,25 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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/*
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* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
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* DDR type: DDR3 / DDR3L
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* DDR width: 32bits
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* DDR density: 8Gb
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* System frequency: 533000Khz
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* Relaxed Timing Mode: false
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* Address mapping type: RBC
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*
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* STM32MP157C ED1 BOARD configuration
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* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 32
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* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
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* DDR density 8
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* timing mode optimized
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* Scheduling/QoS options : type = 2
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* address mapping : RBC
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* Tc > + 85C : N
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* Save Date: 2020.02.20, save Time: 18:49:33
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*/
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#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x40000000
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#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x40000000
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#define DDR_MSTR 0x00040401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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@ -84,6 +73,15 @@
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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