mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
- mips: vocore2: fix SPL image generation
- mips: vocore2: fix LZMA decompression errors - mips: vocore2: fix console output - mips: pic32mzda: fix DTC warnings and GPIO nodes - mips: pic32mzda: make GPIO and MMC working again -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAl9qeQMACgkQKPlOlyTy XBjZ4g/7BZK324Yxqw07JweHExVV5Em3Nh6UysMM7pjsVLKDXDxNlpipjcTDa7uP Dabiw6yzP/xMzC80ZvTxCiU8HsqkgFgETb1dSXHOvHdKJHfP0QleECtSiAXNwvit 58z4cyUl+Mf5vunqy1tfcussgmuWudd8eW0Nxo9YjGUJ5h8TrzO4h5pIfmdV3Til awqbmFWEVBUgM75zUOCc9cCJ2J1et8l9+e/o1XXSGDDDZB7ww5TSIbPG6qLJNflB ghv0FmFJ3SnDwdNL0jxx1iOMsSkF0k5Cpv3aX6LVSYRSWX2+BD1Ec3bPXW8okErd kcnjcqsOKCpNDoqYRyWFdjOXiKcpLPt7k6rO23qwH3/UJExl5wT/XiBkUch7GEVQ n5m0gJXGGVxZolpVo57FRnE372oSiH9GAJ6MIC+5+sLBXWsjK95Z+ZT5dpk7vDB1 3/Uxa51uvzu4gGB72nshF5Bxa1tCJaPm2PeBzFrp5gjTpPfudn3IuZJDXasw3JXe jKd/hhh84JRIJBYO4d6PpKgytgebQNlGN9n3tpZTzx39OItY62rTfxDLrl/u10Fb 3FDjItRep4q6HAJcH/jfmCpjV52KwvtuJjeCliWjPIL9b+FcdFNs1cfOw4SzZ0qM Wbp8Dq/I59vwKCwUqkdqCMXbD+KmrU2qjXnYB8wGREVXhrEed2U= =BSI5 -----END PGP SIGNATURE----- Merge tag 'mips-fixes-for-2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips - mips: vocore2: fix SPL image generation - mips: vocore2: fix LZMA decompression errors - mips: vocore2: fix console output - mips: pic32mzda: fix DTC warnings and GPIO nodes - mips: pic32mzda: make GPIO and MMC working again
This commit is contained in:
Tom Rini
commit
55004fa433
8 changed files with 123 additions and 69 deletions
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@ -26,8 +26,13 @@
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips14kc";
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device-type = "cpu";
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reg = <0>;
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};
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};
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@ -40,6 +45,7 @@
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uart1: serial@1f822000 {
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compatible = "microchip,pic32mzda-uart";
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reg = <0x1f822000 0x50>;
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interrupt-parent = <&evic>;
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interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clock PB2CLK>;
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@ -48,6 +54,7 @@
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uart2: serial@1f822200 {
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compatible = "microchip,pic32mzda-uart";
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reg = <0x1f822200 0x50>;
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interrupt-parent = <&evic>;
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interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock PB2CLK>;
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status = "disabled";
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@ -56,6 +63,7 @@
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uart6: serial@1f822a00 {
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compatible = "microchip,pic32mzda-uart";
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reg = <0x1f822a00 0x50>;
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interrupt-parent = <&evic>;
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interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock PB2CLK>;
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status = "disabled";
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@ -69,6 +77,8 @@
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};
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pinctrl: pinctrl@1f801400 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "microchip,pic32mzda-pinctrl";
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reg = <0x1f801400 0x100>, /* in */
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<0x1f801500 0x200>, /* out */
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@ -76,75 +86,72 @@
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reg-names = "ppsin","ppsout","port";
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status = "disabled";
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ranges = <0 0x1f860000 0xa00>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioA: gpio0@0 {
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gpioA: gpio0@1f860000 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x000 0x48>;
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reg = <0x1f860000 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioB: gpio1@100 {
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gpioB: gpio1@1f860100 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x100 0x48>;
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reg = <0x1f860100 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioC: gpio2@200 {
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gpioC: gpio2@1f860200 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x200 0x48>;
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reg = <0x1f860200 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioD: gpio3@300 {
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gpioD: gpio3@1f860300 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x300 0x48>;
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reg = <0x1f860300 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioE: gpio4@400 {
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gpioE: gpio4@1f860400 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x400 0x48>;
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reg = <0x1f860400 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioF: gpio5@500 {
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gpioF: gpio5@1f860500 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x500 0x48>;
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reg = <0x1f860500 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioG: gpio6@600 {
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gpioG: gpio6@1f860600 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x600 0x48>;
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reg = <0x1f860600 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioH: gpio7@700 {
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gpioH: gpio7@1f860700 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x700 0x48>;
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reg = <0x1f860700 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioJ: gpio8@800 {
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gpioJ: gpio9@1f860800 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x800 0x48>;
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reg = <0x1f860800 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioK: gpio9@900 {
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gpioK: gpio10@1f860900 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x900 0x48>;
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reg = <0x1f860900 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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@ -153,6 +160,7 @@
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sdhci: sdhci@1f8ec000 {
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compatible = "microchip,pic32mzda-sdhci";
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reg = <0x1f8ec000 0x100>;
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interrupt-parent = <&evic>;
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interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock REF4CLK>, <&clock PB5CLK>;
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clock-names = "base_clk", "sys_clk";
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@ -164,6 +172,7 @@
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ethernet: ethernet@1f882000 {
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compatible = "microchip,pic32mzda-eth";
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reg = <0x1f882000 0x1000>;
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interrupt-parent = <&evic>;
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interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock PB5CLK>;
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status = "disabled";
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@ -176,6 +185,7 @@
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reg = <0x1f8e3000 0x1000>,
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<0x1f884000 0x1000>;
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reg-names = "mc", "control";
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interrupt-parent = <&evic>;
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interrupts = <132 IRQ_TYPE_EDGE_RISING>,
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<133 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock PB5CLK>;
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@ -40,6 +40,7 @@
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};
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&sdhci {
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microchip,use-sdcd;
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status = "okay";
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};
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@ -59,7 +59,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <25000000>;
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spi-max-frequency = <40000000>;
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reg = <0>;
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};
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};
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@ -27,7 +27,6 @@ CONFIG_CMD_EXT4_WRITE=y
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# CONFIG_EFI_PARTITION is not set
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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# CONFIG_BLK is not set
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CONFIG_CLK=y
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CONFIG_MMC=y
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CONFIG_DM_MMC=y
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@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x04e000
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CONFIG_ENV_SECT_SIZE=0x1000
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CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
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CONFIG_SPL=y
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CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
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CONFIG_ARCH_MTMIPS=y
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@ -6,65 +6,76 @@
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* Andrei Pistirica <andrei.pistirica@microchip.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <sdhci.h>
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#include <linux/errno.h>
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#include <mach/pic32.h>
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#include <clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int pic32_sdhci_get_cd(struct sdhci_host *host)
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{
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/* PIC32 SDHCI CD errata:
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* - set CD_TEST and clear CD_TEST_INS bit
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*/
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sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
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return 0;
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}
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static const struct sdhci_ops pic32_sdhci_ops = {
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.get_cd = pic32_sdhci_get_cd,
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struct pic32_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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static int pic32_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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const void *fdt = gd->fdt_blob;
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u32 f_min_max[2];
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fdt_addr_t addr;
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fdt_size_t size;
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struct clk clk;
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ulong clk_rate;
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int ret;
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addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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host->ioaddr = ioremap(addr, size);
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host->name = dev->name;
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host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
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host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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host->ops = &pic32_sdhci_ops;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
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"clock-freq-min-max", f_min_max, 2);
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if (ret) {
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printf("sdhci: clock-freq-min-max not found\n");
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return ret;
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}
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host->max_clk = f_min_max[1];
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ret = add_sdhci(host, 0, f_min_max[0]);
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ret = clk_get_by_name(dev, "base_clk", &clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&clk);
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clk_free(&clk);
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if (IS_ERR_VALUE(clk_rate))
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return clk_rate;
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host->ioaddr = dev_remap_addr(dev);
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if (!host->ioaddr)
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return -EINVAL;
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host->name = dev->name;
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host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
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host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
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host->max_clk = clk_rate;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
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if (ret)
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return ret;
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host->mmc->priv = host;
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upriv->mmc = host->mmc;
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ret = sdhci_probe(dev);
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if (ret)
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return ret;
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if (!dev_read_bool(dev, "microchip,use-sdcd")) {
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// Use workaround 1 for erratum #15 by default
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u8 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl = (ctrl & ~SDHCI_CTRL_CD_TEST_INS) | SDHCI_CTRL_CD_TEST;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}
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return 0;
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}
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static int pic32_sdhci_bind(struct udevice *dev)
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{
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struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id pic32_sdhci_ids[] = {
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{ .compatible = "microchip,pic32mzda-sdhci" },
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{ }
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|
@ -74,6 +85,9 @@ U_BOOT_DRIVER(pic32_sdhci_drv) = {
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.name = "pic32_sdhci",
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.id = UCLASS_MMC,
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.of_match = pic32_sdhci_ids,
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.ops = &sdhci_ops,
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.bind = pic32_sdhci_bind,
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.probe = pic32_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct pic32_sdhci_plat)
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};
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|
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@ -222,6 +222,31 @@ static void pic32_eth_pin_config(struct udevice *dev)
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pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
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}
|
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|
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static void pic32_sdhci_pin_config(struct udevice *dev)
|
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{
|
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struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
|
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const struct pic32_pin_config configs[] = {
|
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/* SDWP - H2 */
|
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PIN_CONFIG(PIC32_PORT_H, 2, PIN_CONFIG_PIC32_DIGITAL),
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/* SDCD - A0 */
|
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PIN_CONFIG(PIC32_PORT_A, 0, PIN_CONFIG_PIC32_DIGITAL),
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/* SDCMD - D4 */
|
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PIN_CONFIG(PIC32_PORT_D, 4, PIN_CONFIG_PIC32_DIGITAL),
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/* SDCK - A6 */
|
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PIN_CONFIG(PIC32_PORT_A, 6, PIN_CONFIG_PIC32_DIGITAL),
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/* SDDATA0 - G13 */
|
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PIN_CONFIG(PIC32_PORT_G, 13, PIN_CONFIG_PIC32_DIGITAL),
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/* SDDATA1 - G12 */
|
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PIN_CONFIG(PIC32_PORT_G, 12, PIN_CONFIG_PIC32_DIGITAL),
|
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/* SDDATA2 - G14 */
|
||||
PIN_CONFIG(PIC32_PORT_G, 14, PIN_CONFIG_PIC32_DIGITAL),
|
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/* SDDATA3 - A7 */
|
||||
PIN_CONFIG(PIC32_PORT_A, 7, PIN_CONFIG_PIC32_DIGITAL),
|
||||
};
|
||||
|
||||
pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
|
||||
}
|
||||
|
||||
static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
|
||||
{
|
||||
struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
|
|
@ -240,6 +265,9 @@ static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
|
|||
case PERIPH_ID_ETH:
|
||||
pic32_eth_pin_config(dev);
|
||||
break;
|
||||
case PERIPH_ID_SDHCI:
|
||||
pic32_sdhci_pin_config(dev);
|
||||
break;
|
||||
default:
|
||||
debug("%s: unknown-unhandled case\n", __func__);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_PAD_TO 0
|
||||
|
||||
/* Dummy value */
|
||||
#define CONFIG_SYS_UBOOT_BASE 0
|
||||
|
|
@ -34,12 +35,13 @@
|
|||
#define CONFIG_SYS_NS16550_CLK 40000000
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4
|
||||
#define CONFIG_SYS_NS16550_COM3 0xb0000e00
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
|
||||
/* RAM */
|
||||
|
||||
/* Memory usage */
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
|
||||
#define CONFIG_SYS_CBSIZE 512
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue