GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-18 21:21:37 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'master' of git://git.denx.de/u-boot-ti

Browse source
This commit is contained in:
Tom Rini 2014-08-29 13:47:42 -04:00
commit 6defdc0b55
42 changed files with 680 additions and 393 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
arch/arm/cpu/armv7/keystone/clock-k2e.c
View file

@ -17,6 +17,22 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
int dev_speeds[] = {
SPD800,
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD1400,
SPD1350,
SPD1250,
SPD1000,
SPD850,
SPD800
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD

32
arch/arm/cpu/armv7/keystone/clock-k2hk.c
View file

@ -19,6 +19,38 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
int dev_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD800,
SPD800,
SPD800,
SPD800,
SPD800,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
int arm_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD1350,
SPD1400,
SPD800,
SPD1400,
SPD1350,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD

43
arch/arm/cpu/armv7/keystone/clock.c
View file

@ -11,6 +11,8 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
#define MAX_SPEEDS 13
static void wait_for_completion(const struct pll_init_data *data)
{
int i;
@ -218,3 +220,44 @@ void init_plls(int num_pll, struct pll_init_data *config)
for (i = 0; i < num_pll; i++)
init_pll(&config[i]);
}
static int get_max_speed(u32 val, int *speeds)
{
int j;
if (!val)
return speeds[0];
for (j = 1; j < MAX_SPEEDS; j++) {
if (val == 1)
return speeds[j];
val >>= 1;
}
return SPD800;
}
#ifdef CONFIG_SOC_K2HK
static u32 read_efuse_bootrom(void)
{
return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
__raw_readl(KS2_REV1_DEVSPEED);
}
#else
static inline u32 read_efuse_bootrom(void)
{
return __raw_readl(KS2_EFUSE_BOOTROM);
}
#endif
inline int get_max_dev_speed(void)
{
return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
}
#ifndef CONFIG_SOC_K2E
inline int get_max_arm_speed(void)
{
return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
}
#endif

38
arch/arm/cpu/armv7/omap-common/emif-common.c
View file

@ -242,46 +242,10 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
__udelay(130);
}
static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 fifo_reg;
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_1);
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_2);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
/*
* Disable leveling. This is because if leveling is kept
* enabled, then PHY triggers a false leveling during
* EMIF-idle scenario which results in wrong delay
* values getting updated. After this the EMIF becomes
* unaccessible. So disable it after the first time
*/
writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
}
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
{
if (is_omap54xx())
omap5_ddr3_leveling(base, regs);
else
dra7_ddr3_leveling(base, regs);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
@ -1383,7 +1347,7 @@ void sdram_init(void)
}
if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
(!in_sdram && !warm_reset())) {
(!in_sdram && !warm_reset()) && (!is_dra7xx())) {
if (emif1_enabled)
do_bug0039_workaround(EMIF1_BASE);
if (emif2_enabled)

3
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View file

@ -140,6 +140,9 @@ void s_init(void)
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f();
#endif
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif

2
arch/arm/cpu/armv7/omap5/hw_data.c
View file

@ -556,7 +556,7 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrio_1 = 0x84210840,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x000101A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};

60
arch/arm/cpu/armv7/omap5/sdram.c
View file

@ -145,18 +145,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
@ -169,18 +169,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
@ -394,24 +394,24 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x00B000B0,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00BB00BB,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00800080,
0x00800080,
0x00000000,
0x00600020,
0x40010080,
0x08102040,
0x0,
@ -439,7 +439,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00600060,
0x00600060,
0x00600060,
0x0,
0x00000000,
0x00600020,
0x40010080,
0x08102040,

16
arch/arm/include/asm/arch-keystone/clock-k2e.h
View file

@ -56,10 +56,26 @@ enum pll_type_e {
DDR3_PLL,
};
enum {
SPD800,
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD_RSV
};
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}

14
arch/arm/include/asm/arch-keystone/clock-k2hk.h
View file

@ -63,21 +63,35 @@ enum pll_type_e {
DDR3B_PLL,
};
enum {
SPD800,
SPD1000,
SPD1200,
SPD1350,
SPD1400,
SPD_RSV
};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define CORE_PLL_1200 {CORE_PLL, 625, 32, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1}
#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
#define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1}
#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
#define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1}
#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}

4
arch/arm/include/asm/arch-keystone/clock.h
View file

@ -38,12 +38,16 @@ struct pll_init_data {
};
extern const struct keystone_pll_regs keystone_pll_regs[];
extern int dev_speeds[];
extern int arm_speeds[];
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
#endif
#endif

4
arch/arm/include/asm/arch-keystone/hardware.h
View file

@ -138,6 +138,10 @@ typedef volatile unsigned int *dv_reg_p;
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
/* Queue manager */
#define KS2_QM_MANAGER_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000

12
arch/arm/include/asm/arch-omap5/mem.h
View file

@ -46,13 +46,13 @@
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008
#define STNOR_GPMC_CONFIG1 0x00001200
#define STNOR_GPMC_CONFIG2 0x00101000
#define STNOR_GPMC_CONFIG3 0x00030301
#define STNOR_GPMC_CONFIG4 0x10041004
#define STNOR_GPMC_CONFIG5 0x000C1010
#define STNOR_GPMC_CONFIG1 0x00001000
#define STNOR_GPMC_CONFIG2 0x001f1f00
#define STNOR_GPMC_CONFIG3 0x001f1f01
#define STNOR_GPMC_CONFIG4 0x1f011f01
#define STNOR_GPMC_CONFIG5 0x001d1f1f
#define STNOR_GPMC_CONFIG6 0x08070280
#define STNOR_GPMC_CONFIG7 0x00000F48
#define STNOR_GPMC_CONFIG7 0x00000048
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8

6
board/compulab/cm_t54/cm_t54.c
View file

@ -43,7 +43,7 @@ const struct omap_sysinfo sysinfo = {
*/
int board_init(void)
{
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); /* boot param addr */
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
return 0;
}
@ -89,7 +89,7 @@ uint mmc_get_env_part(struct mmc *mmc)
* If booted from eMMC boot partition then force eMMC
* FIRST boot partition to be env storage
*/
if (bootmode == BOOT_DEVICE_MMC2_2)
if (bootmode == BOOT_DEVICE_MMC2)
bootpart = 1;
return bootpart;
@ -169,7 +169,7 @@ static int handle_mac_address(void)
return 0;
ret = cl_eeprom_read_mac_addr(enetaddr);
if (!ret || !is_valid_ether_addr(enetaddr))
if (ret || !is_valid_ether_addr(enetaddr))
generate_mac_addr(enetaddr);
if (!is_valid_ether_addr(enetaddr))

9
board/ti/am335x/Kconfig
View file

@ -20,4 +20,13 @@ config SYS_CONFIG_NAME
string
default "am335x_evm"
config CONS_INDEX
int "UART used for console"
default 1
help
The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
in documentation, etc) available to it. Depending on your specific
board you may want something other than UART0 as for example the IDK
uses UART3 so enter 4 here.
endif

19
board/ti/am335x/board.c
View file

@ -383,24 +383,19 @@ const struct dpll_params *get_dpll_ddr_params(void)
void set_uart_mux_conf(void)
{
#ifdef CONFIG_SERIAL1
#if CONFIG_CONS_INDEX == 1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
#elif CONFIG_CONS_INDEX == 2
enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
#elif CONFIG_CONS_INDEX == 3
enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
#elif CONFIG_CONS_INDEX == 4
enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
#elif CONFIG_CONS_INDEX == 5
enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
#elif CONFIG_CONS_INDEX == 6
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
#endif
}
void set_mux_conf_regs(void)

156
board/ti/am335x/mux.c
View file

@ -171,91 +171,75 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
#endif
{OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
{-1},
};
#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
#elif defined(CONFIG_NOR)
static struct module_pin_mux bone_norcape_pin_mux[] = {
{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
{OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
{OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
{OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
{OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
{OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
{OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
{OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
{OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
{OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
{OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
{OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
{OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
{OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
{OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
{OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
{OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
{OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
{OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
{OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
{-1},
};
#endif
#if defined(CONFIG_NOR_BOOT)
static struct module_pin_mux norboot_pin_mux[] = {
{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
{-1},
};
void enable_norboot_pin_mux(void)
{
configure_module_pin_mux(norboot_pin_mux);
configure_module_pin_mux(bone_norcape_pin_mux);
}
#endif
@ -336,11 +320,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#ifndef CONFIG_NOR
configure_module_pin_mux(mmc1_pin_mux);
#endif
#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_NOR)
configure_module_pin_mux(bone_norcape_pin_mux);
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
} else if (board_is_gp_evm(header)) {
/* General Purpose EVM */
@ -351,19 +336,16 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
if (profile & ~PROFILE_2)
configure_module_pin_mux(i2c1_pin_mux);
/* Profiles 2 & 3 don't have NAND */
#ifdef CONFIG_NAND
if (profile & ~(PROFILE_2 | PROFILE_3))
configure_module_pin_mux(nand_pin_mux);
#endif
else if (profile == PROFILE_2) {
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
}
} else if (board_is_idk(header)) {
/*
* Industrial Motor Control (IDK)
* note: IDK console is on UART3 by default.
* So u-boot mus be build with CONFIG_SERIAL4 and
* CONFIG_CONS_INDEX=4
*/
/* Industrial Motor Control (IDK) */
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_no_cd_pin_mux);
} else if (board_is_evm_sk(header)) {
@ -377,7 +359,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_NOR)
configure_module_pin_mux(bone_norcape_pin_mux);
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
} else {
puts("Unknown board, cannot configure pinmux.");
hang();

1
board/ti/am43xx/board.c
View file

@ -626,6 +626,7 @@ int board_init(void)
modena_init0_bw_integer, modena_init0_watermark_0;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
/* Clear all important bits for DSS errata that may need to be tweaked*/
mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &

43
board/ti/am43xx/mux.c
View file

@ -73,7 +73,38 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
{-1},
};
static struct module_pin_mux qspi_pin_mux[] = {
#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
#endif
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
{-1},
};
#endif
static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
@ -97,12 +128,22 @@ void enable_board_pin_mux(void)
if (board_is_gpevm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#endif
} else if (board_is_sk()) {
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
printf("Error: NAND flash not present on this board\n");
#endif
configure_module_pin_mux(qspi_pin_mux);
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#else
configure_module_pin_mux(qspi_pin_mux);
#endif
}
}

31
board/ti/dra7xx/evm.c
View file

@ -13,6 +13,8 @@
#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
@ -26,6 +28,9 @@
DECLARE_GLOBAL_DATA_PTR;
/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203
const struct omap_sysinfo sysinfo = {
"Board: DRA7xx\n"
};
@ -272,3 +277,29 @@ int board_eth_init(bd_t *bis)
return ret;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
return;
/* Do not enable VTT for DRA722 */
if (omap_revision() == DRA722_ES1_0)
return;
/*
* EVM Rev G and later use gpio7_11 for DDR3 termination.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
int board_early_init_f(void)
{
vtt_regulator_enable();
return 0;
}
#endif

61
board/ti/dra7xx/mux_data.h
View file

@ -21,6 +21,37 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
#if defined(CONFIG_NOR)
/* NOR only pin-mux */
{GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
{GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
{GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
{GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
{GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
{GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
{GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
{GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
{GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
{GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
{GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
{GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
{GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
{GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
{GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
{GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
{GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
{GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
{GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
{GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
{GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
{GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
{GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
{GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
{GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
{GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
{GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
#else
/* eMMC pinmux */
{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
@ -31,6 +62,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
#endif
#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
@ -68,6 +100,33 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{VIN2A_D21, (IEN | M3)},
{VIN2A_D22, (IEN | M3)},
{VIN2A_D23, (IEN | M3)},
#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
/* NAND / NOR pin-mux */
{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
{GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
{GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
{GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
{GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
{GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
{GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
{GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
{GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
{GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
{GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
{GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
{GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
{GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
{GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
{GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
{GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
{GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
{GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
{GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
{GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
{GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
/* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
#else
/* QSPI pin-mux */
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
@ -78,6 +137,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
#endif /* CONFIG_NAND || CONFIG_NOR */
{USB2_DRVVBUS, (M0 | IEN | FSC) },
{SPI1_CS1, (PEN | IDIS | M14) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */

23
board/ti/ks2_evm/board_k2e.c
View file

@ -25,15 +25,30 @@ unsigned int external_clk[ext_clk_count] = {
[usb_clk] = 100000000,
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1200,
PASS_PLL_1000,
static struct pll_init_data core_pll_config[] = {
CORE_PLL_800,
CORE_PLL_850,
CORE_PLL_1000,
CORE_PLL_1250,
CORE_PLL_1350,
CORE_PLL_1400,
CORE_PLL_1500,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
int speed;
speed = get_max_dev_speed();
init_pll(&core_pll_config[speed]);
init_pll(&pa_pll_config);
return 0;
}
#endif

31
board/ti/ks2_evm/board_k2hk.c
View file

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emac_defs.h>
@ -28,12 +29,23 @@ unsigned int external_clk[ext_clk_count] = {
[rp1_clk] = 123456789
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1228,
PASS_PLL_983,
TETRIS_PLL_1200,
static struct pll_init_data core_pll_config[] = {
CORE_PLL_799,
CORE_PLL_999,
CORE_PLL_1200,
};
static struct pll_init_data tetris_pll_config[] = {
TETRIS_PLL_800,
TETRIS_PLL_1000,
TETRIS_PLL_1200,
TETRIS_PLL_1350,
TETRIS_PLL_1400,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
@ -75,7 +87,16 @@ int get_num_eth_ports(void)
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
int speed;
speed = get_max_dev_speed();
init_pll(&core_pll_config[speed]);
init_pll(&pa_pll_config);
speed = get_max_arm_speed();
init_pll(&tetris_pll_config[speed]);
return 0;
}
#endif

12
common/Makefile
View file

@ -219,10 +219,6 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
# environment
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
ifdef CONFIG_SPL_USB_HOST_SUPPORT
obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
@ -230,14 +226,16 @@ endif
ifdef CONFIG_SPL_SATA_SUPPORT
obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
endif
ifneq ($(CONFIG_SPL_NET_SUPPORT),y)
# environment
ifdef CONFIG_SPL_ENV_SUPPORT
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
else
obj-y += env_nowhere.o
endif
endif
# core command

3
configs/am335x_evm_defconfig
View file

@ -1,4 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

3
configs/am335x_evm_nor_defconfig
View file

@ -1,4 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,NOR"
CONFIG_SYS_EXTRA_OPTIONS="NAND,NOR"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

3
configs/am335x_evm_norboot_defconfig
View file

@ -1,3 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="NOR,NOR_BOOT"
CONFIG_CONS_INDEX=1
CONFIG_ARM=y
CONFIG_TARGET_AM335X_EVM=y

3
configs/am335x_evm_spiboot_defconfig
View file

@ -1,4 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

4
configs/am335x_evm_uart1_defconfig
View file

@ -1,4 +0,0 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL2,CONS_INDEX=2,NAND"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

4
configs/am335x_evm_uart2_defconfig
View file

@ -1,4 +0,0 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL3,CONS_INDEX=3,NAND"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

4
configs/am335x_evm_uart3_defconfig
View file

@ -1,4 +0,0 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL4,CONS_INDEX=4,NAND"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

4
configs/am335x_evm_uart4_defconfig
View file

@ -1,4 +0,0 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL5,CONS_INDEX=5,NAND"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

4
configs/am335x_evm_uart5_defconfig
View file

@ -1,4 +0,0 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL6,CONS_INDEX=6,NAND"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

3
configs/am335x_evm_usbspl_defconfig
View file

@ -1,4 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT"
CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y

13
doc/README.cfi
View file

@ -27,3 +27,16 @@ void flash_cmd_reset(flash_info_t *info)
see also:
http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
Config Option
CONFIG_SYS_MAX_FLASH_SECT: Number of sectors available on Flash device
CONFIG_SYS_FLASH_CFI_WIDTH: Data-width of the flash device
CONFIG_CMD_FLASH: Enables Flash command library
CONFIG_FLASH_CFI_DRIVER: Enables CFI Flash driver
CONFIG_FLASH_CFI_MTD: Enables MTD frame work for NOR Flash devices

67
include/configs/am335x_evm.h
View file

@ -61,7 +61,7 @@
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
@ -223,22 +223,20 @@
/* USB gadget RNDIS */
#define CONFIG_SPL_MUSB_NEW_SUPPORT
/* General network SPL, both CPSW and USB gadget RNDIS */
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#endif
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
/* NAND: device related configs */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
@ -252,15 +250,34 @@
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define MTDIDS_DEFAULT "nand0=nand.0"
#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
"128k(NAND.SPL)," \
"128k(NAND.SPL.backup1)," \
"128k(NAND.SPL.backup2)," \
"128k(NAND.SPL.backup3)," \
"256k(NAND.u-boot-spl-os)," \
"1m(NAND.u-boot)," \
"128k(NAND.u-boot-env)," \
"128k(NAND.u-boot-env.backup1)," \
"8m(NAND.kernel)," \
"-(NAND.rootfs)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x001c0000
#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_AM33XX_BCH
#endif
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#endif
#endif
#endif
#endif /* !CONFIG_NAND */
/*
* For NOR boot, we must set this to the start of where NOR is mapped
@ -314,10 +331,10 @@
/* disable EFI partitions and partition UUID support */
#undef CONFIG_PARTITION_UUIDS
#undef CONFIG_EFI_PARTITION
/*
* Disable CPSW SPL support so we fit within the 101KiB limit.
*/
#undef CONFIG_SPL_ETH_SUPPORT
/* General network SPL */
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#endif
/* USB Device Firmware Update support */
@ -399,6 +416,7 @@
#elif defined(CONFIG_EMMC_BOOT)
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
@ -417,23 +435,6 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
/* NAND support */
#ifdef CONFIG_NAND
#define CONFIG_CMD_NAND
#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
"128k(SPL.backup1)," \
"128k(SPL.backup2)," \
"128k(SPL.backup3),1792k(u-boot)," \
"128k(u-boot-spl-os)," \
"128k(u-boot-env),5m(kernel),-(rootfs)"
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#endif
#endif
/*
* NOR Size = 16 MiB
* Number of Sectors/Blocks = 128

64
include/configs/am43xx_evm.h
View file

@ -265,4 +265,68 @@
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SYS_RX_ETH_BUFFER 64
/* NAND support */
#ifdef CONFIG_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_PAGE_SIZE 4096
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* NAND: driver related configs */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define MTDIDS_DEFAULT "nand0=nand.0"
#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
"256k(NAND.SPL)," \
"256k(NAND.SPL.backup1)," \
"256k(NAND.SPL.backup2)," \
"256k(NAND.SPL.backup3)," \
"512k(NAND.u-boot-spl-os)," \
"1m(NAND.u-boot)," \
"256k(NAND.u-boot-env)," \
"256k(NAND.u-boot-env.backup1)," \
"7m(NAND.kernel)," \
"-(NAND.rootfs)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_AM33XX_BCH
#endif
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
#define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
#endif /* !CONFIG_NAND */
#endif /* __CONFIG_AM43XX_EVM_H */

3
include/configs/cm_t54.h
View file

@ -19,6 +19,9 @@
#undef CONFIG_MISC_INIT_R
#undef CONFIG_SPL_OS_BOOT
/* Enable Generic board */
#define CONFIG_SYS_GENERIC_BOARD
/* Device Tree defines */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

89
include/configs/dra7xx_evm.h
View file

@ -13,6 +13,7 @@
#define __CONFIG_DRA7XX_EVM_H
#define CONFIG_DRA7XX
#define CONFIG_BOARD_EARLY_INIT_F
#ifndef CONFIG_QSPI_BOOT
/* MMC ENV related defines */
@ -143,4 +144,92 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* NAND support */
#ifdef CONFIG_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* NAND: driver related configs */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define MTDIDS_DEFAULT "nand0=nand.0"
#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
"128k(NAND.SPL)," \
"128k(NAND.SPL.backup1)," \
"128k(NAND.SPL.backup2)," \
"128k(NAND.SPL.backup3)," \
"256k(NAND.u-boot-spl-os)," \
"1m(NAND.u-boot)," \
"128k(NAND.u-boot-env)," \
"128k(NAND.u-boot-env.backup1)," \
"8m(NAND.kernel)," \
"-(NAND.rootfs)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_AM33XX_BCH
#endif
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#endif
#endif /* !CONFIG_NAND */
/* Parallel NOR Support */
#if defined(CONFIG_NOR)
/* NOR: device related configs */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
/* #define CONFIG_INIT_IGNORE_ERROR */
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_FLASH
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
#ifdef CONFIG_NOR_BOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
"128k(NOR.SPL)," \
"128k(NOR.SPL.backup1)," \
"128k(NOR.SPL.backup2)," \
"128k(NOR.SPL.backup3)," \
"256k(NOR.u-boot-spl-os)," \
"1m(NOR.u-boot)," \
"128k(NOR.u-boot-env)," \
"128k(NOR.u-boot-env.backup1)," \
"8m(NOR.kernel)," \
"-(NOR.rootfs)"
#define CONFIG_ENV_OFFSET 0x001c0000
#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
#endif
#endif /* NOR support */
#endif /* __CONFIG_DRA7XX_EVM_H */

140
include/configs/pcm051.h
View file

@ -19,35 +19,13 @@
#ifndef __CONFIG_PCM051_H
#define __CONFIG_PCM051_H
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#include <asm/arch/omap.h>
#include <configs/ti_am335x_common.h>
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_NO_FLASH
#define MACH_TYPE_PCM051 4144 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
#define CONFIG_OF_LIBFDT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 1
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80007fc0\0" \
@ -104,21 +82,6 @@
#define V_OSCK 25000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_CMD_ECHO
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* memtest works on 8 MB in DRAM after skipping 32MB from
* start addr of ram disk
@ -127,41 +90,13 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
#define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define CONFIG_MTD_DEVICE
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 24000000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_CONS_INDEX 1
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
@ -170,65 +105,26 @@
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_OMAP_GPIO
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
/* CPU */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_IS_NOWHERE
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack.
*/
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL"
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_SPI_BOOT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
@ -236,23 +132,6 @@
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
* header. That is 0x800FFFC0--0x80100000 should not be used for any
* other needs.
*/
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
/* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*
@ -282,17 +161,6 @@
/* Unsupported features */
#undef CONFIG_USE_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB

1
include/configs/tam3517-common.h
View file

@ -17,6 +17,7 @@
#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TEXT_BASE 0x80008000

19
include/configs/ti_armv7_common.h
View file

@ -202,15 +202,18 @@
#define CONFIG_SPL_OS_BOOT
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack. We load U-Boot itself into memory at
* 0x80800000 for legacy reasons (to not conflict with older SPLs). We
* have our BSS be placed 1MiB after this, to allow for the default
* Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
* We have the SPL malloc pool at the end of the BSS area.
* Place the image at the start of the ROM defined image space (per
* CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
* downloaded image area. We initalize DRAM as soon as we can so that
* we can place stack, malloc and BSS there. We load U-Boot itself into
* memory at 0x80800000 for legacy reasons (to not conflict with older
* SPLs). We have our BSS be placed 2MiB after this, to allow for the
* default Linux kernel address of 0x80008000 to work with most sized
* kernels, in the Falcon Mode case. We have the SPL malloc pool at the
* end of the BSS area. We place our stack at 32MiB after the start of
* DRAM to allow room for all of the above.
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20))
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
#endif

6
include/configs/tseries.h
View file

@ -243,8 +243,12 @@
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#elif defined(CONFIG_NAND)
#undef CONFIG_ENV_IS_NOWHERE
/* No NAND env support in SPL */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_ENV_IS_NOWHERE
#else
#define CONFIG_ENV_IS_IN_NAND
#endif
#define CONFIG_ENV_OFFSET 0x120000 /* TODO: Adresse definieren */
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
#else