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dm: exynos: Convert SPI to driver model

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Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.

A few device tree additions are needed to make the SPI flash available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This commit is contained in:
Simon Glass 2014-10-13 23:42:01 -06:00
parent 623b638607
commit 73186c9460
5 changed files with 199 additions and 345 deletions
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8
arch/arm/dts/exynos5250-snow.dts
View file

@ -53,6 +53,14 @@
}; };
}; };
spi@12d30000 {
spi-max-frequency = <50000000>;
firmware_storage_spi: flash@0 {
compatible = "spi-flash";
reg = <0>;
};
};
spi@131b0000 { spi@131b0000 {
spi-max-frequency = <1000000>; spi-max-frequency = <1000000>;
spi-deactivate-delay = <100>; spi-deactivate-delay = <100>;

1
arch/arm/dts/exynos5420-peach-pit.dts
View file

@ -140,6 +140,7 @@
spi@12d30000 { /* spi1 */ spi@12d30000 { /* spi1 */
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
firmware_storage_spi: flash@0 { firmware_storage_spi: flash@0 {
compatible = "spi-flash";
reg = <0>; reg = <0>;
/* /*

3
board/samsung/common/board.c
View file

@ -87,9 +87,6 @@ int board_init(void)
boot_temp_check(); boot_temp_check();
#endif #endif
#ifdef CONFIG_EXYNOS_SPI
spi_init();
#endif
return exynos_init(); return exynos_init();
} }

523
drivers/spi/exynos_spi.c
View file

@ -6,6 +6,8 @@
*/ */
#include <common.h> #include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h> #include <malloc.h>
#include <spi.h> #include <spi.h>
#include <fdtdec.h> #include <fdtdec.h>
@ -19,176 +21,35 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* Information about each SPI controller */ struct exynos_spi_platdata {
struct spi_bus {
enum periph_id periph_id; enum periph_id periph_id;
s32 frequency; /* Default clock frequency, -1 for none */ s32 frequency; /* Default clock frequency, -1 for none */
struct exynos_spi *regs; struct exynos_spi *regs;
int inited; /* 1 if this bus is ready for use */
int node;
uint deactivate_delay_us; /* Delay to wait after deactivate */ uint deactivate_delay_us; /* Delay to wait after deactivate */
}; };
/* A list of spi buses that we know about */ struct exynos_spi_priv {
static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
static unsigned int bus_count;
struct exynos_spi_slave {
struct spi_slave slave;
struct exynos_spi *regs; struct exynos_spi *regs;
unsigned int freq; /* Default frequency */ unsigned int freq; /* Default frequency */
unsigned int mode; unsigned int mode;
enum periph_id periph_id; /* Peripheral ID for this device */ enum periph_id periph_id; /* Peripheral ID for this device */
unsigned int fifo_size; unsigned int fifo_size;
int skip_preamble; int skip_preamble;
struct spi_bus *bus; /* Pointer to our SPI bus info */
ulong last_transaction_us; /* Time of last transaction end */ ulong last_transaction_us; /* Time of last transaction end */
}; };
static struct spi_bus *spi_get_bus(unsigned dev_index)
{
if (dev_index < bus_count)
return &spi_bus[dev_index];
debug("%s: invalid bus %d", __func__, dev_index);
return NULL;
}
static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
{
return container_of(slave, struct exynos_spi_slave, slave);
}
/**
* Setup the driver private data
*
* @param bus ID of the bus that the slave is attached to
* @param cs ID of the chip select connected to the slave
* @param max_hz Required spi frequency
* @param mode Required spi mode (clk polarity, clk phase and
* master or slave)
* @return new device or NULL
*/
struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct exynos_spi_slave *spi_slave;
struct spi_bus *bus;
if (!spi_cs_is_valid(busnum, cs)) {
debug("%s: Invalid bus/chip select %d, %d\n", __func__,
busnum, cs);
return NULL;
}
spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
if (!spi_slave) {
debug("%s: Could not allocate spi_slave\n", __func__);
return NULL;
}
bus = &spi_bus[busnum];
spi_slave->bus = bus;
spi_slave->regs = bus->regs;
spi_slave->mode = mode;
spi_slave->periph_id = bus->periph_id;
if (bus->periph_id == PERIPH_ID_SPI1 ||
bus->periph_id == PERIPH_ID_SPI2)
spi_slave->fifo_size = 64;
else
spi_slave->fifo_size = 256;
spi_slave->skip_preamble = 0;
spi_slave->last_transaction_us = timer_get_us();
spi_slave->freq = bus->frequency;
if (max_hz)
spi_slave->freq = min(max_hz, spi_slave->freq);
return &spi_slave->slave;
}
/**
* Free spi controller
*
* @param slave Pointer to spi_slave to which controller has to
* communicate with
*/
void spi_free_slave(struct spi_slave *slave)
{
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
free(spi_slave);
}
/** /**
* Flush spi tx, rx fifos and reset the SPI controller * Flush spi tx, rx fifos and reset the SPI controller
* *
* @param slave Pointer to spi_slave to which controller has to * @param regs Pointer to SPI registers
* communicate with
*/ */
static void spi_flush_fifo(struct spi_slave *slave) static void spi_flush_fifo(struct exynos_spi *regs)
{ {
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
struct exynos_spi *regs = spi_slave->regs;
clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
} }
/**
* Initialize the spi base registers, set the required clock frequency and
* initialize the gpios
*
* @param slave Pointer to spi_slave to which controller has to
* communicate with
* @return zero on success else a negative value
*/
int spi_claim_bus(struct spi_slave *slave)
{
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
struct exynos_spi *regs = spi_slave->regs;
u32 reg = 0;
int ret;
ret = set_spi_clk(spi_slave->periph_id,
spi_slave->freq);
if (ret < 0) {
debug("%s: Failed to setup spi clock\n", __func__);
return ret;
}
exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
spi_flush_fifo(slave);
reg = readl(&regs->ch_cfg);
reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
if (spi_slave->mode & SPI_CPHA)
reg |= SPI_CH_CPHA_B;
if (spi_slave->mode & SPI_CPOL)
reg |= SPI_CH_CPOL_L;
writel(reg, &regs->ch_cfg);
writel(SPI_FB_DELAY_180, &regs->fb_clk);
return 0;
}
/**
* Reset the spi H/W and flush the tx and rx fifos
*
* @param slave Pointer to spi_slave to which controller has to
* communicate with
*/
void spi_release_bus(struct spi_slave *slave)
{
spi_flush_fifo(slave);
}
static void spi_get_fifo_levels(struct exynos_spi *regs, static void spi_get_fifo_levels(struct exynos_spi *regs,
int *rx_lvl, int *tx_lvl) int *rx_lvl, int *tx_lvl)
{ {
@ -208,6 +69,8 @@ static void spi_get_fifo_levels(struct exynos_spi *regs,
*/ */
static void spi_request_bytes(struct exynos_spi *regs, int count, int step) static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
{ {
debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
/* For word address we need to swap bytes */ /* For word address we need to swap bytes */
if (step == 4) { if (step == 4) {
setbits_le32(&regs->mode_cfg, setbits_le32(&regs->mode_cfg,
@ -230,10 +93,10 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt); writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
} }
static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
void **dinp, void const **doutp, unsigned long flags) void **dinp, void const **doutp, unsigned long flags)
{ {
struct exynos_spi *regs = spi_slave->regs; struct exynos_spi *regs = priv->regs;
uchar *rxp = *dinp; uchar *rxp = *dinp;
const uchar *txp = *doutp; const uchar *txp = *doutp;
int rx_lvl, tx_lvl; int rx_lvl, tx_lvl;
@ -245,8 +108,8 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
out_bytes = in_bytes = todo; out_bytes = in_bytes = todo;
stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) && stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
!(spi_slave->mode & SPI_SLAVE); !(priv->mode & SPI_SLAVE);
/* /*
* Try to transfer words if we can. This helps read performance at * Try to transfer words if we can. This helps read performance at
@ -254,7 +117,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
*/ */
step = 1; step = 1;
if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) && if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
!spi_slave->skip_preamble) !priv->skip_preamble)
step = 4; step = 4;
/* /*
@ -279,7 +142,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
* Don't completely fill the txfifo, since we don't want our * Don't completely fill the txfifo, since we don't want our
* rxfifo to overflow, and it may already contain data. * rxfifo to overflow, and it may already contain data.
*/ */
while (tx_lvl < spi_slave->fifo_size/2 && out_bytes) { while (tx_lvl < priv->fifo_size/2 && out_bytes) {
if (!txp) if (!txp)
temp = -1; temp = -1;
else if (step == 4) else if (step == 4)
@ -295,9 +158,9 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
if (rx_lvl >= step) { if (rx_lvl >= step) {
while (rx_lvl >= step) { while (rx_lvl >= step) {
temp = readl(&regs->rx_data); temp = readl(&regs->rx_data);
if (spi_slave->skip_preamble) { if (priv->skip_preamble) {
if (temp == SPI_PREAMBLE_END_BYTE) { if (temp == SPI_PREAMBLE_END_BYTE) {
spi_slave->skip_preamble = 0; priv->skip_preamble = 0;
stopping = 0; stopping = 0;
} }
} else { } else {
@ -326,7 +189,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
txp = NULL; txp = NULL;
spi_request_bytes(regs, toread, step); spi_request_bytes(regs, toread, step);
} }
if (spi_slave->skip_preamble && get_timer(start) > 100) { if (priv->skip_preamble && get_timer(start) > 100) {
printf("SPI timeout: in_bytes=%d, out_bytes=%d, ", printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
in_bytes, out_bytes); in_bytes, out_bytes);
return -1; return -1;
@ -340,20 +203,125 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
} }
/** /**
* Transfer and receive data * Activate the CS by driving it LOW
* *
* @param slave Pointer to spi_slave to which controller has to * @param slave Pointer to spi_slave to which controller has to
* communicate with * communicate with
* @param bitlen No of bits to tranfer or receive
* @param dout Pointer to transfer buffer
* @param din Pointer to receive buffer
* @param flags Flags for transfer begin and end
* @return zero on success else a negative value
*/ */
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, static void spi_cs_activate(struct udevice *dev)
void *din, unsigned long flags)
{ {
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); struct udevice *bus = dev->parent;
struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
if (pdata->deactivate_delay_us &&
priv->last_transaction_us) {
ulong delay_us; /* The delay completed so far */
delay_us = timer_get_us() - priv->last_transaction_us;
if (delay_us < pdata->deactivate_delay_us)
udelay(pdata->deactivate_delay_us - delay_us);
}
clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
debug("Activate CS, bus '%s'\n", bus->name);
priv->skip_preamble = priv->mode & SPI_PREAMBLE;
}
/**
* Deactivate the CS by driving it HIGH
*
* @param slave Pointer to spi_slave to which controller has to
* communicate with
*/
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
/* Remember time of this transaction so we can honour the bus delay */
if (pdata->deactivate_delay_us)
priv->last_transaction_us = timer_get_us();
debug("Deactivate CS, bus '%s'\n", bus->name);
}
static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
{
struct exynos_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
plat->periph_id = pinmux_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: Invalid peripheral ID %d\n", __func__,
plat->periph_id);
return -FDT_ERR_NOTFOUND;
}
/* Use 500KHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
500000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->regs, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
return 0;
}
static int exynos_spi_probe(struct udevice *bus)
{
struct exynos_spi_platdata *plat = dev_get_platdata(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
if (plat->periph_id == PERIPH_ID_SPI1 ||
plat->periph_id == PERIPH_ID_SPI2)
priv->fifo_size = 64;
else
priv->fifo_size = 256;
priv->skip_preamble = 0;
priv->last_transaction_us = timer_get_us();
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
return 0;
}
static int exynos_spi_claim_bus(struct udevice *bus)
{
struct exynos_spi_priv *priv = dev_get_priv(bus);
exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
spi_flush_fifo(priv->regs);
writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
return 0;
}
static int exynos_spi_release_bus(struct udevice *bus)
{
struct exynos_spi_priv *priv = dev_get_priv(bus);
spi_flush_fifo(priv->regs);
return 0;
}
static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
struct exynos_spi_priv *priv = dev_get_priv(bus);
int upto, todo; int upto, todo;
int bytelen; int bytelen;
int ret = 0; int ret = 0;
@ -366,7 +334,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
/* Start the transaction, if necessary. */ /* Start the transaction, if necessary. */
if ((flags & SPI_XFER_BEGIN)) if ((flags & SPI_XFER_BEGIN))
spi_cs_activate(slave); spi_cs_activate(dev);
/* /*
* Exynos SPI limits each transfer to 65535 transfers. To keep * Exynos SPI limits each transfer to 65535 transfers. To keep
@ -376,16 +344,16 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
bytelen = bitlen / 8; bytelen = bitlen / 8;
for (upto = 0; !ret && upto < bytelen; upto += todo) { for (upto = 0; !ret && upto < bytelen; upto += todo) {
todo = min(bytelen - upto, (1 << 16) - 4); todo = min(bytelen - upto, (1 << 16) - 4);
ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags); ret = spi_rx_tx(priv, todo, &din, &dout, flags);
if (ret) if (ret)
break; break;
} }
/* Stop the transaction, if necessary. */ /* Stop the transaction, if necessary. */
if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) { if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
spi_cs_deactivate(slave); spi_cs_deactivate(dev);
if (spi_slave->skip_preamble) { if (priv->skip_preamble) {
assert(!spi_slave->skip_preamble); assert(!priv->skip_preamble);
debug("Failed to complete premable transaction\n"); debug("Failed to complete premable transaction\n");
ret = -1; ret = -1;
} }
@ -394,190 +362,69 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
return ret; return ret;
} }
/** static int exynos_spi_set_speed(struct udevice *bus, uint speed)
* Validates the bus and chip select numbers
*
* @param bus ID of the bus that the slave is attached to
* @param cs ID of the chip select connected to the slave
* @return one on success else zero
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{ {
return spi_get_bus(bus) && cs == 0; struct exynos_spi_platdata *plat = bus->platdata;
} struct exynos_spi_priv *priv = dev_get_priv(bus);
int ret;
/** if (speed > plat->frequency)
* Activate the CS by driving it LOW speed = plat->frequency;
* ret = set_spi_clk(priv->periph_id, speed);
* @param slave Pointer to spi_slave to which controller has to if (ret)
* communicate with return ret;
*/ priv->freq = speed;
void spi_cs_activate(struct spi_slave *slave) debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
{
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
/* If it's too soon to do another transaction, wait */
if (spi_slave->bus->deactivate_delay_us &&
spi_slave->last_transaction_us) {
ulong delay_us; /* The delay completed so far */
delay_us = timer_get_us() - spi_slave->last_transaction_us;
if (delay_us < spi_slave->bus->deactivate_delay_us)
udelay(spi_slave->bus->deactivate_delay_us - delay_us);
}
clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
debug("Activate CS, bus %d\n", spi_slave->slave.bus);
spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
}
/**
* Deactivate the CS by driving it HIGH
*
* @param slave Pointer to spi_slave to which controller has to
* communicate with
*/
void spi_cs_deactivate(struct spi_slave *slave)
{
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
/* Remember time of this transaction so we can honour the bus delay */
if (spi_slave->bus->deactivate_delay_us)
spi_slave->last_transaction_us = timer_get_us();
debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
}
static inline struct exynos_spi *get_spi_base(int dev_index)
{
if (dev_index < 3)
return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
else
return (struct exynos_spi *)samsung_get_base_spi_isp() +
(dev_index - 3);
}
/*
* Read the SPI config from the device tree node.
*
* @param blob FDT blob to read from
* @param node Node offset to read from
* @param bus SPI bus structure to fill with information
* @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
*/
#ifdef CONFIG_OF_CONTROL
static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
{
bus->node = node;
bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
bus->periph_id = pinmux_decode_periph_id(blob, node);
if (bus->periph_id == PERIPH_ID_NONE) {
debug("%s: Invalid peripheral ID %d\n", __func__,
bus->periph_id);
return -FDT_ERR_NOTFOUND;
}
/* Use 500KHz as a suitable default */
bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
500000);
bus->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
return 0; return 0;
} }
/* static int exynos_spi_set_mode(struct udevice *bus, uint mode)
* Process a list of nodes, adding them to our list of SPI ports.
*
* @param blob fdt blob
* @param node_list list of nodes to process (any <=0 are ignored)
* @param count number of nodes to process
* @param is_dvc 1 if these are DVC ports, 0 if standard I2C
* @return 0 if ok, -1 on error
*/
static int process_nodes(const void *blob, int node_list[], int count)
{ {
int i; struct exynos_spi_priv *priv = dev_get_priv(bus);
uint32_t reg;
/* build the i2c_controllers[] for each controller */ reg = readl(&priv->regs->ch_cfg);
for (i = 0; i < count; i++) { reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
int node = node_list[i];
struct spi_bus *bus;
if (node <= 0) if (mode & SPI_CPHA)
continue; reg |= SPI_CH_CPHA_B;
bus = &spi_bus[i]; if (mode & SPI_CPOL)
if (spi_get_config(blob, node, bus)) { reg |= SPI_CH_CPOL_L;
printf("exynos spi_init: failed to decode bus %d\n",
i);
return -1;
}
debug("spi: controller bus %d at %p, periph_id %d\n", writel(reg, &priv->regs->ch_cfg);
i, bus->regs, bus->periph_id); priv->mode = mode;
bus->inited = 1; debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
bus_count++;
}
return 0; return 0;
} }
#endif
/** static const struct dm_spi_ops exynos_spi_ops = {
* Set up a new SPI slave for an fdt node .claim_bus = exynos_spi_claim_bus,
* .release_bus = exynos_spi_release_bus,
* @param blob Device tree blob .xfer = exynos_spi_xfer,
* @param node SPI peripheral node to use .set_speed = exynos_spi_set_speed,
* @return 0 if ok, -1 on error .set_mode = exynos_spi_set_mode,
/*
* cs_info is not needed, since we require all chip selects to be
* in the device tree explicitly
*/ */
struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, };
int spi_node)
{
struct spi_bus *bus;
unsigned int i;
for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) { static const struct udevice_id exynos_spi_ids[] = {
if (bus->node == spi_node) { .compatible = "samsung,exynos-spi" },
return spi_base_setup_slave_fdt(blob, i, slave_node); { }
} };
debug("%s: Failed to find bus node %d\n", __func__, spi_node); U_BOOT_DRIVER(exynos_spi) = {
return NULL; .name = "exynos_spi",
} .id = UCLASS_SPI,
.of_match = exynos_spi_ids,
/* Sadly there is no error return from this function */ .ops = &exynos_spi_ops,
void spi_init(void) .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
{ .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
int count; .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
.per_child_auto_alloc_size = sizeof(struct spi_slave),
#ifdef CONFIG_OF_CONTROL .probe = exynos_spi_probe,
int node_list[EXYNOS5_SPI_NUM_CONTROLLERS]; };
const void *blob = gd->fdt_blob;
count = fdtdec_find_aliases_for_id(blob, "spi",
COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
EXYNOS5_SPI_NUM_CONTROLLERS);
if (process_nodes(blob, node_list, count))
return;
#else
struct spi_bus *bus;
for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
bus = &spi_bus[count];
bus->regs = get_spi_base(count);
bus->periph_id = PERIPH_ID_SPI0 + count;
/* Although Exynos5 supports upto 50Mhz speed,
* we are setting it to 10Mhz for safe side
*/
bus->frequency = 10000000;
bus->inited = 1;
bus->node = 0;
bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
}
#endif
}

1
include/configs/exynos-common.h
View file

@ -21,6 +21,7 @@
#define CONFIG_CMD_DM #define CONFIG_CMD_DM
#define CONFIG_DM_GPIO #define CONFIG_DM_GPIO
#define CONFIG_DM_SERIAL #define CONFIG_DM_SERIAL
#define CONFIG_DM_SPI
#define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_CPUINFO