Merge git://git.denx.de/u-boot-fsl-qoriq

This commit is contained in:
Tom Rini 2017-04-04 09:17:08 -04:00
commit 797f165f7a
42 changed files with 691 additions and 133 deletions

View file

@ -73,6 +73,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009203
select ARCH_EARLY_INIT_R select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F select BOARD_EARLY_INIT_F
@ -134,6 +135,8 @@ config FSL_LS_PPA
choice choice
prompt "FSL Layerscape PPA firmware loading-media select" prompt "FSL Layerscape PPA firmware loading-media select"
depends on FSL_LS_PPA depends on FSL_LS_PPA
default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
default SYS_LS_PPA_FW_IN_XIP default SYS_LS_PPA_FW_IN_XIP
config SYS_LS_PPA_FW_IN_XIP config SYS_LS_PPA_FW_IN_XIP
@ -142,13 +145,27 @@ config SYS_LS_PPA_FW_IN_XIP
Say Y here if the PPA firmware locate at XIP flash, such Say Y here if the PPA firmware locate at XIP flash, such
as NOR or QSPI flash. as NOR or QSPI flash.
config SYS_LS_PPA_FW_IN_MMC
bool "eMMC or SD Card"
help
Say Y here if the PPA firmware locate at eMMC/SD card.
config SYS_LS_PPA_FW_IN_NAND
bool "NAND"
help
Say Y here if the PPA firmware locate at NAND flash.
endchoice endchoice
config SYS_LS_PPA_FW_ADDR config SYS_LS_PPA_FW_ADDR
hex "Address of PPA firmware loading from" hex "Address of PPA firmware loading from"
depends on FSL_LS_PPA depends on FSL_LS_PPA
default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
default 0x60500000 if SYS_LS_PPA_FW_IN_XIP default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
default 0x500000 if SYS_LS_PPA_FW_IN_MMC
default 0x500000 if SYS_LS_PPA_FW_IN_NAND
help help
If the PPA firmware locate at XIP flash, such as NOR or If the PPA firmware locate at XIP flash, such as NOR or
QSPI flash, this address is a directly memory-mapped. QSPI flash, this address is a directly memory-mapped.
@ -307,6 +324,9 @@ config SYS_FSL_ERRATUM_A008585
config SYS_FSL_ERRATUM_A008850 config SYS_FSL_ERRATUM_A008850
bool bool
config SYS_FSL_ERRATUM_A009203
bool
config SYS_FSL_ERRATUM_A009635 config SYS_FSL_ERRATUM_A009635
bool bool

View file

@ -89,6 +89,49 @@ static inline void early_mmu_setup(void)
set_sctlr(get_sctlr() | CR_M); set_sctlr(get_sctlr() | CR_M);
} }
static void fix_pcie_mmu_map(void)
{
#ifdef CONFIG_LS2080A
unsigned int i;
u32 svr, ver;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
/* Fix PCIE base and size for LS2088A */
if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
(ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
for (i = 0; i < ARRAY_SIZE(final_map); i++) {
switch (final_map[i].phys) {
case CONFIG_SYS_PCIE1_PHYS_ADDR:
final_map[i].phys = 0x2000000000ULL;
final_map[i].virt = 0x2000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
case CONFIG_SYS_PCIE2_PHYS_ADDR:
final_map[i].phys = 0x2800000000ULL;
final_map[i].virt = 0x2800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
case CONFIG_SYS_PCIE3_PHYS_ADDR:
final_map[i].phys = 0x3000000000ULL;
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
case CONFIG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
default:
break;
}
}
}
#endif
}
/* /*
* The final tables look similar to early tables, but different in detail. * The final tables look similar to early tables, but different in detail.
* These tables are in DRAM. Sub tables are added to enable cache for * These tables are in DRAM. Sub tables are added to enable cache for
@ -103,6 +146,9 @@ static inline void final_mmu_setup(void)
unsigned int el = current_el(); unsigned int el = current_el();
int index; int index;
/* fix the final_map before filling in the block entries */
fix_pcie_mmu_map();
mem_map = final_map; mem_map = final_map;
/* Update mapping for DDR to actual size */ /* Update mapping for DDR to actual size */
@ -436,7 +482,14 @@ int arch_early_init_r(void)
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
erratum_a009635(); u32 svr_dev_id;
/*
* erratum A009635 is valid only for LS2080A SoC and
* its personalitiesi
*/
svr_dev_id = get_svr() >> 16;
if (svr_dev_id == SVR_DEV_LS2080A)
erratum_a009635();
#endif #endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
erratum_a009942_check_cpo(); erratum_a009942_check_cpo();

View file

@ -387,8 +387,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob); fdt_fixup_fman_firmware(blob);
#endif #endif
#ifndef CONFIG_LS1012A
fsl_fdt_disable_usb(blob); fsl_fdt_disable_usb(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
fdt_fixup_gic(blob); fdt_fixup_gic(blob);
#endif #endif

View file

@ -23,6 +23,11 @@ int xfi_dpmac[XFI8 + 1];
int sgmii_dpmac[SGMII16 + 1]; int sgmii_dpmac[SGMII16 + 1];
#endif #endif
__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
{
return;
}
int is_serdes_configured(enum srds_prtcl device) int is_serdes_configured(enum srds_prtcl device)
{ {
int ret = 0; int ret = 0;
@ -46,20 +51,22 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[28]); u32 cfg = 0;
int i; int i;
switch (sd) { switch (sd) {
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
case FSL_SRDS_1: case FSL_SRDS_1:
cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
break; break;
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
case FSL_SRDS_2: case FSL_SRDS_2:
cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
break; break;
#endif #endif
default: default:
@ -78,8 +85,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
return -ENODEV; return -ENODEV;
} }
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg; u32 cfg;
@ -90,7 +97,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift; cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
@ -106,28 +113,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
#ifdef CONFIG_FSL_MC_ENET #ifdef CONFIG_FSL_MC_ENET
switch (lane_prtcl) { switch (lane_prtcl) {
case QSGMII_A: case QSGMII_A:
wriop_init_dpmac(sd, 5, (int)lane_prtcl);
wriop_init_dpmac(sd, 6, (int)lane_prtcl);
wriop_init_dpmac(sd, 7, (int)lane_prtcl);
wriop_init_dpmac(sd, 8, (int)lane_prtcl);
break;
case QSGMII_B: case QSGMII_B:
wriop_init_dpmac(sd, 1, (int)lane_prtcl);
wriop_init_dpmac(sd, 2, (int)lane_prtcl);
wriop_init_dpmac(sd, 3, (int)lane_prtcl);
wriop_init_dpmac(sd, 4, (int)lane_prtcl);
break;
case QSGMII_C: case QSGMII_C:
wriop_init_dpmac(sd, 13, (int)lane_prtcl);
wriop_init_dpmac(sd, 14, (int)lane_prtcl);
wriop_init_dpmac(sd, 15, (int)lane_prtcl);
wriop_init_dpmac(sd, 16, (int)lane_prtcl);
break;
case QSGMII_D: case QSGMII_D:
wriop_init_dpmac(sd, 9, (int)lane_prtcl); wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
wriop_init_dpmac(sd, 10, (int)lane_prtcl);
wriop_init_dpmac(sd, 11, (int)lane_prtcl);
wriop_init_dpmac(sd, 12, (int)lane_prtcl);
break; break;
default: default:
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
@ -165,15 +154,17 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1, serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map); serdes1_prtcl_map);
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2, serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map); serdes2_prtcl_map);
#endif #endif
} }

View file

@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#include <common.h> #include <common.h>
#include <malloc.h>
#include <config.h> #include <config.h>
#include <errno.h> #include <errno.h>
#include <asm/system.h> #include <asm/system.h>
@ -21,9 +22,17 @@
#include <fsl_validate.h> #include <fsl_validate.h>
#endif #endif
#ifdef CONFIG_SYS_LS_PPA_FW_IN_NAND
#include <nand.h>
#elif defined(CONFIG_SYS_LS_PPA_FW_IN_MMC)
#include <mmc.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int ppa_init(void) int ppa_init(void)
{ {
const void *ppa_fit_addr; void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h; u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
int ret; int ret;
@ -34,10 +43,137 @@ int ppa_init(void)
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR; ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
debug("%s: PPA image load from XIP\n", __func__);
#else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */
size_t fw_length, fdt_header_len = sizeof(struct fdt_header);
/* Copy PPA image from MMC/SD/NAND to allocated memory */
#ifdef CONFIG_SYS_LS_PPA_FW_IN_MMC
struct mmc *mmc;
int dev = CONFIG_SYS_MMC_ENV_DEV;
struct fdt_header *fitp;
u32 cnt;
u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
debug("%s: PPA image load from eMMC/SD\n", __func__);
ret = mmc_initialize(gd->bd);
if (ret) {
printf("%s: mmc_initialize() failed\n", __func__);
return ret;
}
mmc = find_mmc_device(dev);
if (!mmc) {
printf("PPA: MMC cannot find device for PPA firmware\n");
return -ENODEV;
}
ret = mmc_init(mmc);
if (ret) {
printf("%s: mmc_init() failed\n", __func__);
return ret;
}
fitp = malloc(roundup(fdt_header_len, 512));
if (!fitp) {
printf("PPA: malloc failed for FIT header(size 0x%zx)\n",
roundup(fdt_header_len, 512));
return -ENOMEM;
}
cnt = DIV_ROUND_UP(fdt_header_len, 512);
debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
__func__, dev, blk, cnt);
ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp);
if (ret != cnt) {
free(fitp);
printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
CONFIG_SYS_LS_PPA_FW_ADDR);
return -EIO;
}
/* flush cache after read */
flush_cache((ulong)fitp, cnt * 512);
ret = fdt_check_header(fitp);
if (ret) {
free(fitp);
printf("%s: fdt_check_header() failed\n", __func__);
return ret;
}
fw_length = fdt_totalsize(fitp);
free(fitp);
fw_length = roundup(fw_length, 512);
ppa_fit_addr = malloc(fw_length);
if (!ppa_fit_addr) {
printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
fw_length);
return -ENOMEM;
}
cnt = DIV_ROUND_UP(fw_length, 512);
debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
__func__, dev, blk, cnt);
ret = mmc->block_dev.block_read(&mmc->block_dev,
blk, cnt, ppa_fit_addr);
if (ret != cnt) {
free(ppa_fit_addr);
printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
CONFIG_SYS_LS_PPA_FW_ADDR);
return -EIO;
}
/* flush cache after read */
flush_cache((ulong)ppa_fit_addr, cnt * 512);
#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
struct fdt_header fit;
debug("%s: PPA image load from NAND\n", __func__);
nand_init();
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fdt_header_len, (u_char *)&fit);
if (ret == -EUCLEAN) {
printf("NAND read of PPA FIT header at offset 0x%x failed\n",
CONFIG_SYS_LS_PPA_FW_ADDR);
return -EIO;
}
ret = fdt_check_header(&fit);
if (ret) {
printf("%s: fdt_check_header() failed\n", __func__);
return ret;
}
fw_length = fdt_totalsize(&fit);
ppa_fit_addr = malloc(fw_length);
if (!ppa_fit_addr) {
printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
fw_length);
return -ENOMEM;
}
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
&fw_length, (u_char *)ppa_fit_addr);
if (ret == -EUCLEAN) {
free(ppa_fit_addr);
printf("NAND read of PPA firmware at offset 0x%x failed\n",
CONFIG_SYS_LS_PPA_FW_ADDR);
return -EIO;
}
/* flush cache after read */
flush_cache((ulong)ppa_fit_addr, fw_length);
#else #else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
#endif #endif
#endif
#ifdef CONFIG_CHAIN_OF_TRUST #ifdef CONFIG_CHAIN_OF_TRUST
ppa_img_addr = (uintptr_t)ppa_fit_addr; ppa_img_addr = (uintptr_t)ppa_fit_addr;
if (fsl_check_boot_mode_secure() != 0) { if (fsl_check_boot_mode_secure() != 0) {
@ -65,5 +201,10 @@ int ppa_init(void)
boot_loc_ptr_l, boot_loc_ptr_h); boot_loc_ptr_l, boot_loc_ptr_h);
ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h); ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
free(ppa_fit_addr);
#endif
return ret; return ret;
} }

View file

@ -152,6 +152,7 @@ static void erratum_rcw_src(void)
* This erratum requires setting glitch_en bit to enable * This erratum requires setting glitch_en bit to enable
* digital glitch filter to improve clock stability. * digital glitch filter to improve clock stability.
*/ */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void) static void erratum_a009203(void)
{ {
u8 __iomem *ptr; u8 __iomem *ptr;
@ -178,6 +179,7 @@ static void erratum_a009203(void)
#endif #endif
#endif #endif
} }
#endif
void bypass_smmu(void) void bypass_smmu(void)
{ {
@ -191,7 +193,9 @@ void fsl_lsch3_early_init_f(void)
{ {
erratum_rcw_src(); erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */ init_early_memctl_regs(); /* tighten IFC timing */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
erratum_a009203(); erratum_a009203();
#endif
erratum_a008514(); erratum_a008514();
erratum_a008336(); erratum_a008336();
#ifdef CONFIG_CHAIN_OF_TRUST #ifdef CONFIG_CHAIN_OF_TRUST

View file

@ -114,7 +114,7 @@
reg = <0x0 0x1550000 0x0 0x10000>, reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x4000000>; <0x0 0x40000000 0x0 0x4000000>;
reg-names = "QuadSPI", "QuadSPI-memory"; reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>; num-cs = <1>;
big-endian; big-endian;
status = "disabled"; status = "disabled";
}; };

View file

@ -48,10 +48,10 @@ enum srds_prtcl {
SGMII14, SGMII14,
SGMII15, SGMII15,
SGMII16, SGMII16,
QSGMII_A, /* A indicates MACs 1-4 */ QSGMII_A,
QSGMII_B, /* B indicates MACs 5-8 */ QSGMII_B,
QSGMII_C, /* C indicates MACs 9-12 */ QSGMII_C,
QSGMII_D, /* D indicates MACs 12-16 */ QSGMII_D,
SERDES_PRCTL_COUNT SERDES_PRCTL_COUNT
}; };

View file

@ -230,10 +230,19 @@ struct ccsr_gur {
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
#if defined(CONFIG_ARCH_LS2080A)
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#endif
#define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400 #define RCW_SB_EN_MASK 0x00000400

View file

@ -7,10 +7,7 @@
#ifndef __FSL_PPA_H_ #ifndef __FSL_PPA_H_
#define __FSL_PPA_H_ #define __FSL_PPA_H_
#define SEC_FIRMWARE_FIT_IMAGE "firmware" #ifdef CONFIG_FSL_LS_PPA
#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1"
#define SEC_FIRMWARE_TARGET_EL 2
int ppa_init(void); int ppa_init(void);
#endif
#endif #endif

View file

@ -0,0 +1,63 @@
/*
* Copyright 2017 NXP Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __FSL_STREAM_ID_H
#define __FSL_STREAM_ID_H
/*
* Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
* are not hardwired and are programmed by sw. There are a limited number
* of stream IDs available, and the partitioning of them is scenario
* dependent. This header defines the partitioning between legacy, PCI,
* and DPAA1 devices.
*
* This partitioning can be customized in this file depending
* on the specific hardware config:
*
* -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
* -all legacy devices get a unique stream ID assigned and programmed in
* their AMQR registers by u-boot
*
* -PCIe
* -there is a range of stream IDs set aside for PCI in this
* file. U-boot will scan the PCI bus and for each device discovered:
* -allocate a streamID
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
* -set a msi-map entry in the PEXn controller node in the
* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
* for more info on the msi-map definition)
* -set a iommu-map entry in the PEXn controller node in the
* device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
* for more info on the iommu-map definition)
*
* -DPAA1
* - Stream ids for DPAA1 use are reserved for future usecase.
*
*/
#define FSL_INVALID_STREAM_ID 0
/* legacy devices */
#define FSL_USB1_STREAM_ID 1
#define FSL_USB2_STREAM_ID 2
#define FSL_USB3_STREAM_ID 3
#define FSL_SDHC_STREAM_ID 4
#define FSL_SATA_STREAM_ID 5
#define FSL_QE_STREAM_ID 6
#define FSL_QDMA_STREAM_ID 7
#define FSL_EDMA_STREAM_ID 8
#define FSL_ETR_STREAM_ID 9
/* PCI - programmed in PEXn_LUT */
#define FSL_PEX_STREAM_ID_START 11
#define FSL_PEX_STREAM_ID_END 26
/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
#define FSL_DPAA1_STREAM_ID_START 27
#define FSL_DPAA1_STREAM_ID_END 63
#endif

View file

@ -8,11 +8,11 @@
#define __FSL_STREAM_ID_H #define __FSL_STREAM_ID_H
/* /*
* Stream IDs on ls2080a devices are not hardwired and are * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
* programmed by sw. There are a limited number of stream IDs * devices are not hardwired and are programmed by sw. There are a limited
* available, and the partitioning of them is scenario dependent. * number of stream IDs available, and the partitioning of them is scenario
* This header defines the partitioning between legacy, PCI, * dependent. This header defines the partitioning between legacy,
* and DPAA2 devices. * PCI, and DPAA2 devices.
* *
* This partitioning can be customized in this file depending * This partitioning can be customized in this file depending
* on the specific hardware config: * on the specific hardware config:
@ -29,6 +29,9 @@
* -set a msi-map entry in the PEXn controller node in the * -set a msi-map entry in the PEXn controller node in the
* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
* for more info on the msi-map definition) * for more info on the msi-map definition)
* -set a iommu-map entry in the PEXn controller node in the
* device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
* for more info on the iommu-map definition)
* *
* -DPAA2 * -DPAA2
* -u-boot will allocate a range of stream IDs to be used by the Management * -u-boot will allocate a range of stream IDs to be used by the Management
@ -36,7 +39,7 @@
* -the MC is responsible for allocating and setting up 'isolation context * -the MC is responsible for allocating and setting up 'isolation context
* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
* *
* On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
* each of the different bus masters. The relationship between * each of the different bus masters. The relationship between
* the AMQ registers and stream IDs is defined in the table below: * the AMQ registers and stream IDs is defined in the table below:
* AMQ bit streamID bit * AMQ bit streamID bit

View file

@ -7,10 +7,6 @@
#ifndef __SEC_FIRMWARE_H_ #ifndef __SEC_FIRMWARE_H_
#define __SEC_FIRMWARE_H_ #define __SEC_FIRMWARE_H_
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
int sec_firmware_init(const void *, u32 *, u32 *); int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *); bool sec_firmware_is_valid(const void *);

View file

@ -38,11 +38,11 @@
* in boot ROM of the SoC. * in boot ROM of the SoC.
* The feature is only applicable in case of NOR boot and is * The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI). * not applicable in case of RAMBOOT (NAND, SD, SPI).
* For LS, this feature is available for all device if IE Table
* is copied to XIP memory
* Also, for LS, ISBC doesn't verify this table.
*/ */
#ifndef CONFIG_ESBC_HDR_LS
/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT #define CONFIG_FSL_ISBC_KEY_EXT
#endif
#endif #endif
@ -112,6 +112,8 @@
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
#ifdef CONFIG_LS1043A #ifdef CONFIG_LS1043A
#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000 #define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
#elif defined(CONFIG_FSL_LSCH3)
#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x580c40000
#endif #endif
#else #else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"

View file

@ -27,6 +27,10 @@
#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
((key_len) == 2 * KEY_SIZE_BYTES)) ((key_len) == 2 * KEY_SIZE_BYTES))
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
/* Global data structure */
static struct fsl_secboot_glb glb;
#endif
/* This array contains DER value for SHA-256 */ /* This array contains DER value for SHA-256 */
static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
@ -60,7 +64,7 @@ self:
#if defined(CONFIG_FSL_ISBC_KEY_EXT) #if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 check_ie(struct fsl_secboot_img_priv *img) static u32 check_ie(struct fsl_secboot_img_priv *img)
{ {
if (img->hdr.ie_flag) if (img->hdr.ie_flag & IE_FLAG_MASK)
return 1; return 1;
return 0; return 0;
@ -119,7 +123,21 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
} }
#endif #endif
static int get_ie_info_addr(u32 *ie_addr) #if defined(CONFIG_ESBC_HDR_LS)
static int get_ie_info_addr(uintptr_t *ie_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
/* For LS-CH3, the address of IE Table is
* stated in Scratch13 and scratch14 of DCFG.
* Bootrom validates this table while validating uboot.
* DCFG is LE*/
*ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]);
*ie_addr = *ie_addr << 32;
*ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]);
return 0;
}
#else /* CONFIG_ESBC_HDR_LS */
static int get_ie_info_addr(uintptr_t *ie_addr)
{ {
struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl; struct fsl_secboot_sg_table *sg_tbl;
@ -147,16 +165,17 @@ static int get_ie_info_addr(u32 *ie_addr)
/* IE Key Table is the first entry in the SG Table */ /* IE Key Table is the first entry in the SG Table */
#if defined(CONFIG_MPC85xx) #if defined(CONFIG_MPC85xx)
*ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) + *ie_addr = (uintptr_t)((sg_tbl->src_addr &
flash_base_addr; ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else #else
*ie_addr = sg_tbl->src_addr; *ie_addr = (uintptr_t)sg_tbl->src_addr;
#endif #endif
debug("IE Table address is %x\n", *ie_addr); debug("IE Table address is %lx\n", *ie_addr);
return 0; return 0;
} }
#endif /* CONFIG_ESBC_HDR_LS */
#endif #endif
#ifdef CONFIG_KEY_REVOCATION #ifdef CONFIG_KEY_REVOCATION
@ -164,7 +183,10 @@ static int get_ie_info_addr(u32 *ie_addr)
static u32 check_srk(struct fsl_secboot_img_priv *img) static u32 check_srk(struct fsl_secboot_img_priv *img)
{ {
#ifdef CONFIG_ESBC_HDR_LS #ifdef CONFIG_ESBC_HDR_LS
/* In LS, No SRK Flag as SRK is always present*/ /* In LS, No SRK Flag as SRK is always present if IE not present*/
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
return !check_ie(img);
#endif
return 1; return 1;
#else #else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
@ -253,14 +275,29 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
#endif /* CONFIG_ESBC_HDR_LS */ #endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT) #if defined(CONFIG_FSL_ISBC_KEY_EXT)
static void install_ie_tbl(uintptr_t ie_tbl_addr,
struct fsl_secboot_img_priv *img)
{
/* Copy IE tbl to Global Data */
memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info));
img->ie_addr = (uintptr_t)&glb.ie_tbl;
glb.ie_addr = img->ie_addr;
}
static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
{ {
struct fsl_secboot_img_hdr *hdr = &img->hdr; struct fsl_secboot_img_hdr *hdr = &img->hdr;
u32 ie_key_len, ie_revoc_flag, ie_num; u32 ie_key_len, ie_revoc_flag, ie_num;
struct ie_key_info *ie_info; struct ie_key_info *ie_info;
if (get_ie_info_addr(&img->ie_addr)) if (!img->ie_addr) {
return ERROR_IE_TABLE_NOT_FOUND; if (get_ie_info_addr(&img->ie_addr))
return ERROR_IE_TABLE_NOT_FOUND;
else
install_ie_tbl(img->ie_addr, img);
}
ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
if (ie_info->num_keys == 0 || ie_info->num_keys > 32) if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
@ -786,6 +823,26 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
return 0; return 0;
} }
/* Function to initialize img priv and global data structure
*/
static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
{
*img_ptr = malloc(sizeof(struct fsl_secboot_img_priv));
struct fsl_secboot_img_priv *img = *img_ptr;
if (!img)
return -ENOMEM;
memset(img, 0, sizeof(struct fsl_secboot_img_priv));
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
if (glb.ie_addr)
img->ie_addr = glb.ie_addr;
#endif
return 0;
}
/* haddr - Address of the header of image to be validated. /* haddr - Address of the header of image to be validated.
* arg_hash_str - Option hash string. If provided, this * arg_hash_str - Option hash string. If provided, this
* overrides the key hash in the SFP fuses. * overrides the key hash in the SFP fuses.
@ -839,12 +896,9 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
hash_cmd = 1; hash_cmd = 1;
} }
img = malloc(sizeof(struct fsl_secboot_img_priv)); ret = secboot_init(&img);
if (ret)
if (!img) goto exit;
return -1;
memset(img, 0, sizeof(struct fsl_secboot_img_priv));
/* Update the information in Private Struct */ /* Update the information in Private Struct */
hdr = &img->hdr; hdr = &img->hdr;
@ -899,5 +953,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
} }
exit: exit:
/* Free Img as it was malloc'ed*/
free(img);
return ret; return ret;
} }

View file

@ -23,9 +23,7 @@
#ifdef CONFIG_U_QE #ifdef CONFIG_U_QE
#include <fsl_qe.h> #include <fsl_qe.h>
#endif #endif
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h> #include <asm/arch/ppa.h>
#endif
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;

View file

@ -19,6 +19,8 @@
#include <asm/arch/soc.h> #include <asm/arch/soc.h>
#include <hwconfig.h> #include <hwconfig.h>
#include <fsl_sec.h> #include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include "../common/qixis.h" #include "../common/qixis.h"
#include "ls2080aqds_qixis.h" #include "ls2080aqds_qixis.h"
@ -225,6 +227,14 @@ int board_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
rtc_enable_32khz_output(); rtc_enable_32khz_output();
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0; return 0;
} }
@ -266,9 +276,6 @@ void detail_board_ddr_info(void)
#if defined(CONFIG_ARCH_MISC_INIT) #if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void) int arch_misc_init(void)
{ {
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0; return 0;
} }
#endif #endif

View file

@ -19,6 +19,7 @@
#include <i2c.h> #include <i2c.h>
#include <asm/arch/mmu.h> #include <asm/arch/mmu.h>
#include <asm/arch/soc.h> #include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
#include <fsl_sec.h> #include <fsl_sec.h>
#include "../common/qixis.h" #include "../common/qixis.h"
@ -181,10 +182,17 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
#ifdef CONFIG_FSL_MC_ENET #ifdef CONFIG_FSL_MC_ENET
/* invert AQR405 IRQ pins polarity */ /* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif #endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0; return 0;
} }
@ -223,9 +231,6 @@ void detail_board_ddr_info(void)
#if defined(CONFIG_ARCH_MISC_INIT) #if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void) int arch_misc_init(void)
{ {
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0; return 0;
} }
#endif #endif

View file

@ -426,6 +426,7 @@ static int initr_nand(void)
{ {
puts("NAND: "); puts("NAND: ");
nand_init(); nand_init();
printf("%lu MiB\n", nand_size() / 1024);
return 0; return 0;
} }
#endif #endif

View file

@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y CONFIG_NAND_BOOT=y

View file

@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y CONFIG_SD_BOOT=y

View file

@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT" CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
CONFIG_SD_BOOT=y CONFIG_SD_BOOT=y

View file

@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y CONFIG_SD_BOOT=y

View file

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y CONFIG_TARGET_LS2080AQDS=y
CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
# CONFIG_SYS_MALLOC_F is not set # CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y CONFIG_FIT=y

View file

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y CONFIG_TARGET_LS2080ARDB=y
CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
# CONFIG_SYS_MALLOC_F is not set # CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y CONFIG_FIT=y

View file

@ -131,8 +131,23 @@ static void create_mtd_concat(void)
} }
#endif #endif
unsigned long nand_size(void)
{
return total_nand_size;
}
void nand_init(void) void nand_init(void)
{ {
static int initialized;
/*
* Avoid initializing NAND Flash multiple times,
* otherwise it will calculate a wrong total size.
*/
if (initialized)
return;
initialized = 1;
#ifdef CONFIG_SYS_NAND_SELF_INIT #ifdef CONFIG_SYS_NAND_SELF_INIT
board_nand_init(); board_nand_init();
#else #else
@ -142,8 +157,6 @@ void nand_init(void)
nand_init_chip(i); nand_init_chip(i);
#endif #endif
printf("%lu MiB\n", total_nand_size / 1024);
#ifdef CONFIG_SYS_NAND_SELECT_DEVICE #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
/* /*
* Select the chip in the board/cpu specific driver * Select the chip in the board/cpu specific driver

View file

@ -79,3 +79,33 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
return PHY_INTERFACE_MODE_NONE; return PHY_INTERFACE_MODE_NONE;
} }
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
{
switch (lane_prtcl) {
case QSGMII_A:
wriop_init_dpmac(sd, 5, (int)lane_prtcl);
wriop_init_dpmac(sd, 6, (int)lane_prtcl);
wriop_init_dpmac(sd, 7, (int)lane_prtcl);
wriop_init_dpmac(sd, 8, (int)lane_prtcl);
break;
case QSGMII_B:
wriop_init_dpmac(sd, 1, (int)lane_prtcl);
wriop_init_dpmac(sd, 2, (int)lane_prtcl);
wriop_init_dpmac(sd, 3, (int)lane_prtcl);
wriop_init_dpmac(sd, 4, (int)lane_prtcl);
break;
case QSGMII_C:
wriop_init_dpmac(sd, 13, (int)lane_prtcl);
wriop_init_dpmac(sd, 14, (int)lane_prtcl);
wriop_init_dpmac(sd, 15, (int)lane_prtcl);
wriop_init_dpmac(sd, 16, (int)lane_prtcl);
break;
case QSGMII_D:
wriop_init_dpmac(sd, 9, (int)lane_prtcl);
wriop_init_dpmac(sd, 10, (int)lane_prtcl);
wriop_init_dpmac(sd, 11, (int)lane_prtcl);
wriop_init_dpmac(sd, 12, (int)lane_prtcl);
break;
}
}

View file

@ -167,6 +167,27 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
pci_get_regions(pcie->bus, &io, &mem, &pref); pci_get_regions(pcie->bus, &io, &mem, &pref);
idx = PCIE_ATU_REGION_INDEX1 + 1; idx = PCIE_ATU_REGION_INDEX1 + 1;
/* Fix the pcie memory map for LS2088A series SoCs */
svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A) {
if (io)
io->phys_start = (io->phys_start &
(PCIE_PHYS_SIZE - 1)) +
LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
if (mem)
mem->phys_start = (mem->phys_start &
(PCIE_PHYS_SIZE - 1)) +
LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
if (pref)
pref->phys_start = (pref->phys_start &
(PCIE_PHYS_SIZE - 1)) +
LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
}
if (io) if (io)
/* ATU : OUTBOUND : IO */ /* ATU : OUTBOUND : IO */
ls_pcie_atu_outbound_set(pcie, idx++, ls_pcie_atu_outbound_set(pcie, idx++,
@ -409,6 +430,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
} }
static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
{
ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
}
static void ls_pcie_setup_ep(struct ls_pcie *pcie) static void ls_pcie_setup_ep(struct ls_pcie *pcie)
{ {
u32 sriov; u32 sriov;
@ -432,6 +458,8 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie)
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
ls_pcie_ep_setup_atu(pcie); ls_pcie_ep_setup_atu(pcie);
} }
ls_pcie_ep_enable_cfg(pcie);
} }
static int ls_pcie_probe(struct udevice *dev) static int ls_pcie_probe(struct udevice *dev)
@ -442,6 +470,7 @@ static int ls_pcie_probe(struct udevice *dev)
u8 header_type; u8 header_type;
u16 link_sta; u16 link_sta;
bool ep_mode; bool ep_mode;
uint svr;
int ret; int ret;
pcie->bus = dev; pcie->bus = dev;
@ -495,6 +524,19 @@ static int ls_pcie_probe(struct udevice *dev)
return ret; return ret;
} }
/*
* Fix the pcie memory map address and PF control registers address
* for LS2088A series SoCs
*/
svr = get_svr();
svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A) {
pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
pcie->ctrl = pcie->lut + 0x40000;
}
pcie->cfg0 = map_physmem(pcie->cfg_res.start, pcie->cfg0 = map_physmem(pcie->cfg_res.start,
fdt_resource_size(&pcie->cfg_res), fdt_resource_size(&pcie->cfg_res),
MAP_NOCACHE); MAP_NOCACHE);

View file

@ -26,6 +26,10 @@
#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
#endif #endif
#define PCIE_PHYS_SIZE 0x200000000
#define LS2088A_PCIE_PHYS_SIZE 0x800000000
#define LS2088A_PCIE1_PHYS_ADDR 0x2000000000
/* iATU registers */ /* iATU registers */
#define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND (0x1 << 31) #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
@ -94,8 +98,10 @@
#define PCIE_LUT_ENTRY_COUNT 32 #define PCIE_LUT_ENTRY_COUNT 32
/* PF Controll registers */ /* PF Controll registers */
#define PCIE_PF_CONFIG 0x14
#define PCIE_PF_VF_CTRL 0x7F8 #define PCIE_PF_VF_CTRL 0x7F8
#define PCIE_PF_DBG 0x7FC #define PCIE_PF_DBG 0x7FC
#define PCIE_CONFIG_READY (1 << 0)
#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx)) #define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
#define PCIE_SYS_BASE_ADDR 0x3400000 #define PCIE_SYS_BASE_ADDR 0x3400000
@ -107,6 +113,10 @@
#define SVR_LS102XA 0 #define SVR_LS102XA 0
#define SVR_VAR_PER_SHIFT 8 #define SVR_VAR_PER_SHIFT 8
#define SVR_LS102XA_MASK 0x700 #define SVR_LS102XA_MASK 0x700
#define SVR_LS2088A 0x870900
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
/* LS1021a PCIE space */ /* LS1021a PCIE space */
#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL

View file

@ -15,7 +15,7 @@
#include <fdt_support.h> #include <fdt_support.h>
#include "pcie_layerscape.h" #include "pcie_layerscape.h"
#ifdef CONFIG_FSL_LSCH3 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/* /*
* Return next available LUT index. * Return next available LUT index.
*/ */
@ -72,19 +72,26 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
u32 *prop; u32 *prop;
u32 phandle; u32 phandle;
int nodeoffset; int nodeoffset;
uint svr;
char *compat = NULL;
/* find pci controller node */ /* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
pcie->dbi_res.start); pcie->dbi_res.start);
if (nodeoffset < 0) { if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A)
compat = "fsl,ls2088a-pcie";
else
compat = CONFIG_FSL_PCIE_COMPAT;
if (compat)
nodeoffset = fdt_node_offset_by_compat_reg(blob,
compat, pcie->dbi_res.start);
#endif
if (nodeoffset < 0) if (nodeoffset < 0)
return; return;
#else
return;
#endif
} }
/* get phandle to MSI controller */ /* get phandle to MSI controller */
@ -103,6 +110,58 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
} }
/*
* An iommu-map is a property to be added to the pci controller
* node. It is a table, where each entry consists of 4 fields
* e.g.:
*
* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
*/
static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
u32 devid, u32 streamid)
{
u32 *prop;
u32 iommu_map[4];
int nodeoffset;
int lenp;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
pcie->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
nodeoffset = fdt_node_offset_by_compat_reg(blob,
CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
if (nodeoffset < 0)
return;
#else
return;
#endif
}
/* get phandle to iommu controller */
prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
if (prop == NULL) {
debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
__func__, pcie->idx);
return;
}
/* set iommu-map row */
iommu_map[0] = cpu_to_fdt32(devid);
iommu_map[1] = *++prop;
iommu_map[2] = cpu_to_fdt32(streamid);
iommu_map[3] = cpu_to_fdt32(1);
if (devid == 0) {
fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
iommu_map, 16);
} else {
fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
}
}
static void fdt_fixup_pcie(void *blob) static void fdt_fixup_pcie(void *blob)
{ {
struct udevice *dev, *bus; struct udevice *dev, *bus;
@ -139,6 +198,9 @@ static void fdt_fixup_pcie(void *blob)
/* update msi-map in device tree */ /* update msi-map in device tree */
fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
streamid); streamid);
/* update iommu-map in device tree */
fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
streamid);
} }
} }
#endif #endif
@ -146,19 +208,25 @@ static void fdt_fixup_pcie(void *blob)
static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
{ {
int off; int off;
uint svr;
char *compat = NULL;
off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
pcie->dbi_res.start); pcie->dbi_res.start);
if (off < 0) { if (off < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
off = fdt_node_offset_by_compat_reg(blob, svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
CONFIG_FSL_PCIE_COMPAT, if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
pcie->dbi_res.start); svr == SVR_LS2048A || svr == SVR_LS2044A)
compat = "fsl,ls2088a-pcie";
else
compat = CONFIG_FSL_PCIE_COMPAT;
if (compat)
off = fdt_node_offset_by_compat_reg(blob,
compat, pcie->dbi_res.start);
#endif
if (off < 0) if (off < 0)
return; return;
#else
return;
#endif
} }
if (pcie->enabled) if (pcie->enabled)
@ -175,7 +243,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
list_for_each_entry(pcie, &ls_pcie_list, list) list_for_each_entry(pcie, &ls_pcie_list, list)
ft_pcie_ls_setup(blob, pcie); ft_pcie_ls_setup(blob, pcie);
#ifdef CONFIG_FSL_LSCH3 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
fdt_fixup_pcie(blob); fdt_fixup_pcie(blob);
#endif #endif
} }

View file

@ -1037,8 +1037,11 @@ static int fsl_qspi_probe(struct udevice *bus)
* setting the size of these devices to 0. This would ensure * setting the size of these devices to 0. This would ensure
* that the complete memory map is assigned to only one flash device. * that the complete memory map is assigned to only one flash device.
*/ */
qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]); qspi_write32(priv->flags, &priv->regs->sfa1ad,
priv->amba_base[0] + amba_size_per_chip);
switch (priv->num_chipselect) { switch (priv->num_chipselect) {
case 1:
break;
case 2: case 2:
qspi_write32(priv->flags, &priv->regs->sfa2ad, qspi_write32(priv->flags, &priv->regs->sfa2ad,
priv->amba_base[1]); priv->amba_base[1]);

View file

@ -11,6 +11,7 @@
#define CONFIG_GICV2 #define CONFIG_GICV2
#include <asm/arch/config.h> #include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
#define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_SUPPORT_RAW_INITRD

View file

@ -13,6 +13,7 @@
#define CONFIG_MP #define CONFIG_MP
#define CONFIG_GICV2 #define CONFIG_GICV2
#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h> #include <asm/arch/config.h>
/* Link Definitions */ /* Link Definitions */
@ -187,12 +188,14 @@
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)" "5m(kernel),1m(dtb),9m(file_system)"
#else #else
#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ "2m@0x100000(nor_bank0_uboot),"\
"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ "40m@0x1100000(nor_bank0_fit)," \
"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ "7m(nor_bank0_user)," \
"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ "2m@0x4100000(nor_bank4_uboot)," \
"40m(nor_bank4_fit);7e800000.flash:" \ "40m@0x5100000(nor_bank4_fit),"\
"-(nor_bank4_user);" \
"7e800000.flash:" \
"1m(nand_uboot),1m(nand_uboot_env)," \ "1m(nand_uboot),1m(nand_uboot_env)," \
"20m(nand_fit);spi0.0:1m(uboot)," \ "20m(nand_fit);spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)" "5m(kernel),1m(dtb),9m(file_system)"

View file

@ -13,6 +13,7 @@
#define CONFIG_GICV2 #define CONFIG_GICV2
#include <asm/arch/config.h> #include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
/* Link Definitions */ /* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

View file

@ -485,12 +485,14 @@ unsigned long get_board_ddr_clk(void);
#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
"14m(free)" "14m(free)"
#else #else
#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ "2m@0x100000(nor_bank0_uboot),"\
"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ "40m@0x1100000(nor_bank0_fit)," \
"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ "7m(nor_bank0_user)," \
"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ "2m@0x4100000(nor_bank4_uboot)," \
"40m(nor_bank4_fit);7e800000.flash:" \ "40m@0x5100000(nor_bank4_fit),"\
"-(nor_bank4_user);" \
"7e800000.flash:" \
"4m(nand_uboot),36m(nand_kernel)," \ "4m(nand_uboot),36m(nand_kernel)," \
"472m(nand_free);spi0.0:2m(uboot)," \ "472m(nand_free);spi0.0:2m(uboot)," \
"14m(free)" "14m(free)"

View file

@ -13,7 +13,7 @@
#define CONFIG_GICV3 #define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147 #define CONFIG_FSL_TZPC_BP147
#include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h> #include <asm/arch/config.h>
/* Link Definitions */ /* Link Definitions */

View file

@ -368,6 +368,7 @@ unsigned long get_board_ddr_clk(void);
"kernel_start=0x581100000\0" \ "kernel_start=0x581100000\0" \
"kernel_load=0xa0000000\0" \ "kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \ "kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
"mcinitcmd=esbc_validate 0x580c80000;" \ "mcinitcmd=esbc_validate 0x580c80000;" \
"esbc_validate 0x580cc0000;" \ "esbc_validate 0x580cc0000;" \
"fsl_mc start mc 0x580300000" \ "fsl_mc start mc 0x580300000" \
@ -384,6 +385,7 @@ unsigned long get_board_ddr_clk(void);
"kernel_start=0x581100000\0" \ "kernel_start=0x581100000\0" \
"kernel_load=0xa0000000\0" \ "kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \ "kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
"mcinitcmd=fsl_mc start mc 0x580300000" \ "mcinitcmd=fsl_mc start mc 0x580300000" \
" 0x580800000 \0" " 0x580800000 \0"
#endif /* CONFIG_SECURE_BOOT */ #endif /* CONFIG_SECURE_BOOT */

View file

@ -339,6 +339,7 @@ unsigned long get_board_sys_clk(void);
"kernel_start=0x581100000\0" \ "kernel_start=0x581100000\0" \
"kernel_load=0xa0000000\0" \ "kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \ "kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
"fdtfile=fsl-ls2080a-rdb.dtb\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \
"mcinitcmd=esbc_validate 0x580c80000;" \ "mcinitcmd=esbc_validate 0x580c80000;" \
"esbc_validate 0x580cc0000;" \ "esbc_validate 0x580cc0000;" \
@ -362,6 +363,7 @@ unsigned long get_board_sys_clk(void);
"kernel_start=0x581100000\0" \ "kernel_start=0x581100000\0" \
"kernel_load=0xa0000000\0" \ "kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \ "kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
"fdtfile=fsl-ls2080a-rdb.dtb\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \
"mcinitcmd=fsl_mc start mc 0x580300000" \ "mcinitcmd=fsl_mc start mc 0x580300000" \
" 0x580800000 \0" \ " 0x580800000 \0" \

View file

@ -68,4 +68,5 @@ phy_interface_t wriop_get_enet_if(int);
void wriop_dpmac_disable(int); void wriop_dpmac_disable(int);
void wriop_dpmac_enable(int); void wriop_dpmac_enable(int);
phy_interface_t wriop_dpmac_enet_if(int, int); phy_interface_t wriop_dpmac_enet_if(int, int);
void wriop_init_dpmac_qsgmii(int, int);
#endif /* __LDPAA_WRIOP_H */ #endif /* __LDPAA_WRIOP_H */

View file

@ -40,8 +40,8 @@ struct fsl_secboot_img_hdr {
u8 num_srk; u8 num_srk;
u8 srk_sel; u8 srk_sel;
u8 reserve; u8 reserve;
u8 ie_flag;
} len_kr; } len_kr;
u8 ie_flag;
u32 uid_flag; u32 uid_flag;
@ -69,6 +69,11 @@ struct fsl_secboot_img_hdr {
#define MAX_KEY_ENTRIES 8 #define MAX_KEY_ENTRIES 8
#endif #endif
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#define IE_FLAG_MASK 0x1
#define SCRATCH_IE_LOW_ADR 13
#define SCRATCH_IE_HIGH_ADR 14
#endif
#else /* CONFIG_ESBC_HDR_LS */ #else /* CONFIG_ESBC_HDR_LS */
@ -150,6 +155,10 @@ struct fsl_secboot_img_hdr {
#define MAX_KEY_ENTRIES 4 #define MAX_KEY_ENTRIES 4
#endif #endif
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#define IE_FLAG_MASK 0xFFFFFFFF
#endif
#endif /* CONFIG_ESBC_HDR_LS */ #endif /* CONFIG_ESBC_HDR_LS */
@ -202,6 +211,17 @@ struct fsl_secboot_sg_table {
}; };
#endif #endif
/* ESBC global structure.
* Data to be used across verification of different images.
* Stores follwoing Data:
* IE Table
*/
struct fsl_secboot_glb {
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
uintptr_t ie_addr;
struct ie_key_info ie_tbl;
#endif
};
/* /*
* ESBC private structure. * ESBC private structure.
* Private structure used by ESBC to store following fields * Private structure used by ESBC to store following fields
@ -213,7 +233,7 @@ struct fsl_secboot_sg_table {
*/ */
struct fsl_secboot_img_priv { struct fsl_secboot_img_priv {
uint32_t hdr_location; uint32_t hdr_location;
u32 ie_addr; uintptr_t ie_addr;
u32 key_len; u32 key_len;
struct fsl_secboot_img_hdr hdr; struct fsl_secboot_img_hdr hdr;

View file

@ -28,6 +28,7 @@
#endif #endif
extern void nand_init(void); extern void nand_init(void);
unsigned long nand_size(void);
#include <linux/compat.h> #include <linux/compat.h>
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>

View file

@ -194,17 +194,20 @@ void pbl_load_uboot(int ifd, struct image_tool_params *params)
pbl_parser(params->imagename); pbl_parser(params->imagename);
/* parse the pbi.cfg file. */ /* parse the pbi.cfg file. */
pbl_parser(params->imagename2); if (params->imagename2[0] != '\0')
pbl_parser(params->imagename2);
fp_uboot = fopen(params->datafile, "r"); if (params->datafile) {
if (fp_uboot == NULL) { fp_uboot = fopen(params->datafile, "r");
printf("Error: %s open failed\n", params->datafile); if (fp_uboot == NULL) {
exit(EXIT_FAILURE); printf("Error: %s open failed\n", params->datafile);
exit(EXIT_FAILURE);
}
load_uboot(fp_uboot);
fclose(fp_uboot);
} }
load_uboot(fp_uboot);
add_end_cmd(); add_end_cmd();
fclose(fp_uboot);
lseek(ifd, 0, SEEK_SET); lseek(ifd, 0, SEEK_SET);
size = pbl_size; size = pbl_size;
@ -265,21 +268,24 @@ int pblimage_check_params(struct image_tool_params *params)
if (!params) if (!params)
return EXIT_FAILURE; return EXIT_FAILURE;
fp_uboot = fopen(params->datafile, "r"); if (params->datafile) {
if (fp_uboot == NULL) { fp_uboot = fopen(params->datafile, "r");
printf("Error: %s open failed\n", params->datafile); if (fp_uboot == NULL) {
exit(EXIT_FAILURE); printf("Error: %s open failed\n", params->datafile);
} exit(EXIT_FAILURE);
fd = fileno(fp_uboot); }
fd = fileno(fp_uboot);
if (fstat(fd, &st) == -1) { if (fstat(fd, &st) == -1) {
printf("Error: Could not determine u-boot image size. %s\n", printf("Error: Could not determine u-boot image size. %s\n",
strerror(errno)); strerror(errno));
exit(EXIT_FAILURE); exit(EXIT_FAILURE);
} }
/* For the variable size, we need to pad it to 64 byte boundary */ /* For the variable size, pad it to 64 byte boundary */
uboot_size = roundup(st.st_size, 64); uboot_size = roundup(st.st_size, 64);
fclose(fp_uboot);
}
if (params->arch == IH_ARCH_ARM) { if (params->arch == IH_ARCH_ARM) {
arch_flag = IH_ARCH_ARM; arch_flag = IH_ARCH_ARM;