mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 06:31:31 +00:00
Merge git://git.denx.de/u-boot-riscv
- Correct SYS_TEXT_BASE for qemu. - Support booti. - Increase SYSBOOTM_LEN for Fedora/RISCV kernel. - Support SMP booting from flash.
This commit is contained in:
commit
7d41f2dcbe
19 changed files with 180 additions and 17 deletions
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@ -162,6 +162,13 @@ config SBI_IPI
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default y if RISCV_SMODE
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depends on SMP
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config XIP
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bool "XIP mode"
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help
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XIP (eXecute In Place) is a method for executing code directly
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from a NOR flash memory without copying the code to ram.
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Say yes here if U-Boot boots from flash directly.
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config STACK_SIZE_SHIFT
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int
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default 13
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@ -15,7 +15,10 @@
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* The variables here must be stored in the data section since they are used
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* before the bss section is available.
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*/
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#ifdef CONFIG_OF_PRIOR_STAGE
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phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
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#endif
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#ifndef CONFIG_XIP
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u32 hart_lottery __attribute__((section(".data"))) = 0;
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/*
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@ -23,6 +26,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
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* finished initialization of global data.
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*/
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u32 available_harts_lock = 1;
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#endif
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static inline bool supports_extension(char ext)
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{
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@ -98,6 +98,7 @@ call_board_init_f_0:
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mv sp, a0
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#endif
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#ifndef CONFIG_XIP
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/*
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* Pick hart to initialize global data and run U-Boot. The other harts
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* wait for initialization to complete.
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@ -106,15 +107,21 @@ call_board_init_f_0:
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li s2, 1
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amoswap.w s2, t1, 0(t0)
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bnez s2, wait_for_gd_init
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#else
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bnez tp, secondary_hart_loop
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#endif
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#ifdef CONFIG_OF_PRIOR_STAGE
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la t0, prior_stage_fdt_address
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SREG s1, 0(t0)
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#endif
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jal board_init_f_init_reserve
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/* save the boot hart id to global_data */
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SREG tp, GD_BOOT_HART(gp)
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#ifndef CONFIG_XIP
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la t0, available_harts_lock
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fence rw, w
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amoswap.w zero, zero, 0(t0)
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@ -141,6 +148,7 @@ wait_for_gd_init:
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* secondary_hart_loop.
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*/
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bnez s2, secondary_hart_loop
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#endif
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/* Enable cache */
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jal icache_enable
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@ -27,7 +27,9 @@ struct arch_global_data {
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#ifdef CONFIG_SMP
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struct ipi_data ipi[CONFIG_NR_CPUS];
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#endif
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#ifndef CONFIG_XIP
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ulong available_harts;
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#endif
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};
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#include <asm-generic/global_data.h>
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@ -7,6 +7,7 @@
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# Rick Chen, Andes Technology Corporation <rick@andestech.com>
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obj-$(CONFIG_CMD_BOOTM) += bootm.o
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obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
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obj-$(CONFIG_CMD_GO) += boot.o
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obj-y += cache.o
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obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
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@ -14,7 +14,9 @@
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int main(void)
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{
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DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
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#ifndef CONFIG_XIP
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DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
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#endif
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return 0;
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}
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55
arch/riscv/lib/image.c
Normal file
55
arch/riscv/lib/image.c
Normal file
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@ -0,0 +1,55 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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* Based on arm/lib/image.c
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*/
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#include <common.h>
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#include <mapmem.h>
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#include <errno.h>
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#include <linux/sizes.h>
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#include <linux/stddef.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ASCII version of "RISCV" defined in Linux kernel */
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#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
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struct linux_image_h {
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uint32_t code0; /* Executable code */
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uint32_t code1; /* Executable code */
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uint64_t text_offset; /* Image load offset */
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uint64_t image_size; /* Effective Image size */
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uint64_t res1; /* reserved */
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uint64_t res2; /* reserved */
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uint64_t res3; /* reserved */
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uint64_t magic; /* Magic number */
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uint32_t res4; /* reserved */
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uint32_t res5; /* reserved */
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};
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int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
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bool force_reloc)
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{
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struct linux_image_h *lhdr;
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lhdr = (struct linux_image_h *)map_sysmem(image, 0);
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if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
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puts("Bad Linux RISCV Image magic!\n");
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return -EINVAL;
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}
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if (lhdr->image_size == 0) {
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puts("Image lacks image_size field, error!\n");
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return -EINVAL;
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}
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*size = lhdr->image_size;
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*relocated_addr = gd->ram_base + lhdr->text_offset;
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unmap_sysmem(lhdr);
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return 0;
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}
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@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
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continue;
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}
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#ifndef CONFIG_XIP
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/* skip if hart is not available */
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if (!(gd->arch.available_harts & (1 << reg)))
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continue;
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#endif
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gd->arch.ipi[reg].addr = ipi->addr;
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gd->arch.ipi[reg].arg0 = ipi->arg0;
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@ -5,3 +5,5 @@ F: board/AndesTech/ax25-ae350/
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F: include/configs/ax25-ae350.h
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F: configs/ae350_rv32_defconfig
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F: configs/ae350_rv64_defconfig
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F: configs/ae350_rv32_xip_defconfig
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F: configs/ae350_rv64_xip_defconfig
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@ -67,10 +67,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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void *board_fdt_blob_setup(void)
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{
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void **ptr = (void *)&prior_stage_fdt_address;
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if (fdt_magic(*ptr) == FDT_MAGIC)
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return (void *)*ptr;
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return (void *)CONFIG_SYS_FDT_BASE;
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}
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@ -14,7 +14,8 @@ config SYS_CONFIG_NAME
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config SYS_TEXT_BASE
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default 0x80000000 if !RISCV_SMODE
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default 0x80200000 if RISCV_SMODE
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default 0x80200000 if RISCV_SMODE && ARCH_RV64I
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default 0x80400000 if RISCV_SMODE && ARCH_RV32I
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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@ -223,7 +223,7 @@ config CMD_BOOTZ
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config CMD_BOOTI
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bool "booti"
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depends on ARM64
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depends on ARM64 || RISCV
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default y
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help
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Boot an AArch64 Linux Kernel image from memory.
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@ -77,7 +77,11 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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bootm_disable_interrupts();
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images.os.os = IH_OS_LINUX;
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#ifdef CONFIG_RISCV_SMODE
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images.os.arch = IH_ARCH_RISCV;
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#elif CONFIG_ARM64
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images.os.arch = IH_ARCH_ARM64;
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#endif
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ret = do_bootm_states(cmdtp, flag, argc, argv,
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#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
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BOOTM_STATE_RAMDISK |
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@ -92,7 +96,7 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#ifdef CONFIG_SYS_LONGHELP
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static char booti_help_text[] =
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"[addr [initrd[:size]] [fdt]]\n"
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" - boot arm64 Linux Image stored in memory\n"
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" - boot Linux 'Image' stored at 'addr'\n"
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"\tThe argument 'initrd' is optional and specifies the address\n"
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"\tof an initrd in memory. The optional parameter ':size' allows\n"
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"\tspecifying the size of a RAW initrd.\n"
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U_BOOT_CMD(
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booti, CONFIG_SYS_MAXARGS, 1, do_booti,
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"boot arm64 Linux Image image from memory", booti_help_text
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"boot Linux kernel 'Image' format from memory", booti_help_text
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);
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@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_BOOTP_PREFER_SERVERIP=y
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CONFIG_CMD_CACHE=y
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CONFIG_OF_BOARD=y
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CONFIG_OF_PRIOR_STAGE=y
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CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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37
configs/ae350_rv32_xip_defconfig
Normal file
37
configs/ae350_rv32_xip_defconfig
Normal file
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@ -0,0 +1,37 @@
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CONFIG_RISCV=y
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CONFIG_SYS_TEXT_BASE=0x80000000
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CONFIG_XIP=y
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CONFIG_TARGET_AX25_AE350=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SYS_PROMPT="RISC-V # "
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SF_TEST=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_BOOTP_PREFER_SERVERIP=y
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CONFIG_CMD_CACHE=y
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CONFIG_OF_SEPARATE=y
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CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_MMC=y
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CONFIG_FTSDC010=y
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CONFIG_FTSDC010_SDIO=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_CFI_FLASH=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0x0
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_FTMAC100=y
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CONFIG_BAUDRATE=38400
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_ATCSPI200_SPI=y
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@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_BOOTP_PREFER_SERVERIP=y
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CONFIG_CMD_CACHE=y
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CONFIG_OF_BOARD=y
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CONFIG_OF_PRIOR_STAGE=y
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CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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38
configs/ae350_rv64_xip_defconfig
Normal file
38
configs/ae350_rv64_xip_defconfig
Normal file
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@ -0,0 +1,38 @@
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CONFIG_RISCV=y
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CONFIG_SYS_TEXT_BASE=0x80000000
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CONFIG_XIP=y
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CONFIG_TARGET_AX25_AE350=y
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CONFIG_ARCH_RV64I=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SYS_PROMPT="RISC-V # "
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SF_TEST=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_BOOTP_PREFER_SERVERIP=y
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CONFIG_CMD_CACHE=y
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CONFIG_OF_SEPARATE=y
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CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_MMC=y
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CONFIG_FTSDC010=y
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CONFIG_FTSDC010_SDIO=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_CFI_FLASH=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0x0
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_FTMAC100=y
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CONFIG_BAUDRATE=38400
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_ATCSPI200_SPI=y
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@ -40,7 +40,7 @@
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#define CONFIG_SYS_MALLOC_LEN (512 << 10)
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/* DT blob (fdt) address */
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#define CONFIG_SYS_FDT_BASE 0x000f0000
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#define CONFIG_SYS_FDT_BASE 0x800f0000
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/*
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* Physical Memory Map
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@ -15,7 +15,7 @@
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#define CONFIG_SYS_MALLOC_LEN SZ_8M
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#define CONFIG_SYS_BOOTM_LEN SZ_16M
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
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@ -41,11 +41,15 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x82000000\0" \
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"scriptaddr=0x82100000\0" \
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"pxefile_addr_r=0x82200000\0" \
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"ramdisk_addr_r=0x82300000\0" \
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"kernel_addr_r=0x84000000\0" \
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"fdt_addr_r=0x88000000\0" \
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"scriptaddr=0x88100000\0" \
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"pxefile_addr_r=0x88200000\0" \
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"ramdisk_addr_r=0x88300000\0" \
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BOOTENV
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#define CONFIG_PREBOOT \
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"setenv fdt_addr ${fdtcontroladdr};" \
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"fdt addr ${fdtcontroladdr};"
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#endif /* __CONFIG_H */
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