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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx

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This commit is contained in:
Wolfgang Denk 2008-04-13 09:39:26 -07:00
commit 8258b6e2f5
5 changed files with 6 additions and 6 deletions
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2
board/freescale/mpc837xemds/mpc837xemds.c
View file

@ -36,7 +36,7 @@ int board_early_init_f(void)
u32 spridr = in_be32(&immr->sysconf.spridr);
/* we check only part num, and don't look for CPU revisions */
switch (spridr) {
switch (PARTID_NO_E(spridr)) {
case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);

2
board/freescale/mpc837xerdb/mpc837xerdb.c
View file

@ -16,10 +16,10 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <vsc7385.h>
#if defined(CFG_DRAM_TEST)
int
testdram(void)

4
cpu/mpc83xx/spd_sdram.c
View file

@ -601,7 +601,7 @@ long int spd_sdram()
debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
/* Check DIMM data bus width */
if (spd.dataw_lsb == 0x20) {
if (spd.dataw_lsb < 64) {
if (spd.mem_type == SPD_MEMTYPE_DDR)
burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
else
@ -763,7 +763,7 @@ long int spd_sdram()
sdram_cfg |= SDRAM_CFG_RD_EN;
/* The DIMM is 32bit width */
if (spd.dataw_lsb == 0x20) {
if (spd.dataw_lsb < 64) {
if (spd.mem_type == SPD_MEMTYPE_DDR)
sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
if (spd.mem_type == SPD_MEMTYPE_DDR2)

2
include/configs/MPC837XEMDS.h
View file

@ -96,7 +96,7 @@
*/
#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
#define CFG_SCCR_SATACM SCCR_SATACM_1 /* CSB:SATA[0:3] = 1:1 */
#define CFG_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
/*
* System IO Config

2
include/configs/MPC837XERDB.h
View file

@ -108,7 +108,7 @@
/* System Clock Configuration Register */
#define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
#define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */
#define CFG_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
/*
* System IO Config