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fu740: make WayEnable can be configured by menuconfig

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Signed-off-by:TekkamanV <tekkamanv@starfivetech.com>
This commit is contained in:
TekkamanV 2021-08-07 17:30:21 +08:00 • committed by Tekkaman Ninja
parent d7698efa3d
commit 99e391012d
2 changed files with 24 additions and 3 deletions
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20
arch/riscv/cpu/fu740/Kconfig
View file

@ -42,7 +42,8 @@ config SIFIVE_FU740
config SIFIVE_FU740_L2CC_FLUSH
bool "Support Level 2 Cache Controller Flush operation of SiFive fu740"
if SIFIVE_FU740_L2CC_FLUSH
menu "Level 2 Cache Controller Flush range"
depends on SIFIVE_FU740_L2CC_FLUSH
config SIFIVE_FU740_L2CC_FLUSH_START
hex "Level 2 Cache Flush operation start"
@ -52,4 +53,19 @@ config SIFIVE_FU740_L2CC_FLUSH_SIZE
hex "Level 2 Cache Flush operation size"
default 0x800000000
endif # SIFIVE_FU740_L2CC_FLUSH
endmenu # SIFIVE_FU740_L2CC_FLUSH
config SIFIVE_FU740_L2CC_WAYENABLE_DIY
bool "Config Level 2 Cache Controller: the largest way which has been enabled"
menu "The index of the largest way"
depends on SIFIVE_FU740_L2CC_WAYENABLE_DIY
config SIFIVE_FU740_L2CC_WAYENABLE_DIY_NUM
int "The index of the largest way which has been enabled for level 2 Cache "
default 1
range 0 255
help
Range[0, 255]. The index of the largest way which has been enabled.
endmenu # SIFIVE_FU740_L2CC_WAYENABLE_DIY

7
arch/riscv/cpu/fu740/cache.c
View file

@ -52,7 +52,12 @@ int cache_enable_ways(void)
/* memory barrier */
mb();
(*enable) = ways - 1;
#if CONFIG_IS_ENABLED(SIFIVE_FU740_L2CC_WAYENABLE_DIY)
if (CONFIG_SIFIVE_FU740_L2CC_WAYENABLE_DIY_NUM < ways)
(*enable) = CONFIG_SIFIVE_FU740_L2CC_WAYENABLE_DIY_NUM;
else
#endif //SIFIVE_FU740_L2CC_WAYENABLE_DIY
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;