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spi: zynq_spi: Use clk subsystem to get reference spi clk
Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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parent
6c9662df49
commit
b79a7030c3
1 changed files with 28 additions and 7 deletions
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@ -8,10 +8,12 @@
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#include <common.h>
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#include <common.h>
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#include <dm.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <log.h>
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#include <log.h>
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#include <malloc.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi.h>
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#include <time.h>
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#include <time.h>
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#include <clk.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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@ -79,17 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
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plat->regs = dev_read_addr_ptr(bus);
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plat->regs = dev_read_addr_ptr(bus);
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/* FIXME: Use 250MHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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250000000);
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plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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"spi-deactivate-delay", 0);
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"spi-deactivate-delay", 0);
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plat->activate_delay_us = fdtdec_get_int(blob, node,
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plat->activate_delay_us = fdtdec_get_int(blob, node,
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"spi-activate-delay", 0);
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"spi-activate-delay", 0);
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plat->speed_hz = plat->frequency / 2;
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debug("%s: regs=%p max-frequency=%d\n", __func__,
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plat->regs, plat->frequency);
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return 0;
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return 0;
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}
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}
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@ -128,13 +123,39 @@ static int zynq_spi_probe(struct udevice *bus)
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{
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{
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struct zynq_spi_platdata *plat = dev_get_platdata(bus);
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struct zynq_spi_platdata *plat = dev_get_platdata(bus);
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct clk clk;
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unsigned long clock;
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int ret;
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priv->regs = plat->regs;
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priv->regs = plat->regs;
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priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
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priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
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ret = clk_get_by_name(bus, "ref_clk", &clk);
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if (ret < 0) {
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dev_err(bus, "failed to get clock\n");
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return ret;
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}
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clock = clk_get_rate(&clk);
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if (IS_ERR_VALUE(clock)) {
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dev_err(bus, "failed to get rate\n");
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return clock;
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}
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ret = clk_enable(&clk);
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if (ret && ret != -ENOSYS) {
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dev_err(bus, "failed to enable clock\n");
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return ret;
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}
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/* init the zynq spi hw */
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/* init the zynq spi hw */
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zynq_spi_init_hw(priv);
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zynq_spi_init_hw(priv);
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plat->frequency = clock;
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plat->speed_hz = plat->frequency / 2;
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debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
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return 0;
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return 0;
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}
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}
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