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spi: zynq_spi: Use clk subsystem to get reference spi clk

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Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
T Karthik Reddy 2020-02-04 05:47:44 -07:00 • committed by Michal Simek
parent 6c9662df49
commit b79a7030c3
1 changed files with 28 additions and 7 deletions
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35
drivers/spi/zynq_spi.c
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@ -8,10 +8,12 @@
#include <common.h> #include <common.h>
#include <dm.h> #include <dm.h>
#include <dm/device_compat.h>
#include <log.h> #include <log.h>
#include <malloc.h> #include <malloc.h>
#include <spi.h> #include <spi.h>
#include <time.h> #include <time.h>
#include <clk.h>
#include <asm/io.h> #include <asm/io.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/delay.h> #include <linux/delay.h>
@ -79,17 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
plat->regs = dev_read_addr_ptr(bus); plat->regs = dev_read_addr_ptr(bus);
/* FIXME: Use 250MHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
250000000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node, plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0); "spi-deactivate-delay", 0);
plat->activate_delay_us = fdtdec_get_int(blob, node, plat->activate_delay_us = fdtdec_get_int(blob, node,
"spi-activate-delay", 0); "spi-activate-delay", 0);
plat->speed_hz = plat->frequency / 2;
debug("%s: regs=%p max-frequency=%d\n", __func__,
plat->regs, plat->frequency);
return 0; return 0;
} }
@ -128,13 +123,39 @@ static int zynq_spi_probe(struct udevice *bus)
{ {
struct zynq_spi_platdata *plat = dev_get_platdata(bus); struct zynq_spi_platdata *plat = dev_get_platdata(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus); struct zynq_spi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
int ret;
priv->regs = plat->regs; priv->regs = plat->regs;
priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
ret = clk_get_by_name(bus, "ref_clk", &clk);
if (ret < 0) {
dev_err(bus, "failed to get clock\n");
return ret;
}
clock = clk_get_rate(&clk);
if (IS_ERR_VALUE(clock)) {
dev_err(bus, "failed to get rate\n");
return clock;
}
ret = clk_enable(&clk);
if (ret && ret != -ENOSYS) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
/* init the zynq spi hw */ /* init the zynq spi hw */
zynq_spi_init_hw(priv); zynq_spi_init_hw(priv);
plat->frequency = clock;
plat->speed_hz = plat->frequency / 2;
debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
return 0; return 0;
} }