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arm: at91: pmc: replace the constant with a define in at91_pmc.h
To enable the clocks on the at91 boards a constant (0x4) is used. This is replaced with a define in at91_pmc.h (1 << 2). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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9 changed files with 9 additions and 8 deletions
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@ -158,6 +158,7 @@ typedef struct at91_pmc {
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91_PMC_DDR (1 << 2) /* DDR Clock */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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@ -136,7 +136,7 @@ void mem_init(void)
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
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@ -316,7 +316,7 @@ void mem_init(void)
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* Chip select 1 is for DDR2/SDRAM */
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csa = readl(&matrix->ebicsa);
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@ -353,7 +353,7 @@ void mem_init(void)
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* Chip select 1 is for DDR2/SDRAM */
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csa = readl(&matrix->ebicsa);
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@ -191,7 +191,7 @@ void mem_init(void)
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/* enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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@ -430,7 +430,7 @@ void mem_init(void)
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/* enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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@ -390,7 +390,7 @@ void mem_init(void)
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/* enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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@ -386,7 +386,7 @@ void mem_init(void)
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/* enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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@ -149,7 +149,7 @@ void mem_init(void)
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(0x4, &pmc->scer);
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writel(AT91_PMC_DDR, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
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