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arm: at91: pmc: replace the constant with a define in at91_pmc.h

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To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 <<  2).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Erik van Luijk 2015-08-13 15:43:20 +02:00 • committed by Andreas Bießmann
parent 6560491fe5
commit c982f6b9bf
9 changed files with 9 additions and 8 deletions
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1
arch/arm/mach-at91/include/mach/at91_pmc.h
View file

@ -158,6 +158,7 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91_PMC_DDR (1 << 2) /* DDR Clock */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */

2
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
View file

@ -136,7 +136,7 @@ void mem_init(void)
ddr2_conf(&ddr2);
/* enable DDR2 clock */
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);

2
board/atmel/at91sam9n12ek/at91sam9n12ek.c
View file

@ -316,7 +316,7 @@ void mem_init(void)
ddr2_conf(&ddr2);
/* enable DDR2 clock */
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(&matrix->ebicsa);

2
board/atmel/at91sam9x5ek/at91sam9x5ek.c
View file

@ -353,7 +353,7 @@ void mem_init(void)
ddr2_conf(&ddr2);
/* enable DDR2 clock */
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(&matrix->ebicsa);

2
board/atmel/sama5d3_xplained/sama5d3_xplained.c
View file

@ -191,7 +191,7 @@ void mem_init(void)
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);

2
board/atmel/sama5d3xek/sama5d3xek.c
View file

@ -430,7 +430,7 @@ void mem_init(void)
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);

2
board/atmel/sama5d4_xplained/sama5d4_xplained.c
View file

@ -390,7 +390,7 @@ void mem_init(void)
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);

2
board/atmel/sama5d4ek/sama5d4ek.c
View file

@ -386,7 +386,7 @@ void mem_init(void)
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);

2
board/siemens/corvus/board.c
View file

@ -149,7 +149,7 @@ void mem_init(void)
ddr2_conf(&ddr2);
/* enable DDR2 clock */
writel(0x4, &pmc->scer);
writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);