mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-15 19:51:37 +00:00
Merge branch 'starfive-tech:JH7110_VisionFive2_devel' into Star64
This commit is contained in:
GitHub
commit
ce3fd04a79
37 changed files with 345 additions and 148 deletions
|
|
@ -11,26 +11,43 @@
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|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
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||||
|
||||
static bool check_eeprom_dram_info(phys_size_t size)
|
||||
{
|
||||
switch (size) {
|
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case 0x80000000:
|
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case 0x100000000:
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||||
case 0x200000000:
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case 0x400000000:
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return true;
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default:
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return false;
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}
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}
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int dram_init(void)
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{
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int ret;
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u32 data;
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u8 data;
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u32 len;
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u32 offset;
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phys_size_t size;
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data = 0;
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len = 4;
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offset = 88; /*offset of memory size stored in eeprom*/
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len = 1;
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offset = 91; /*offset of memory size stored in eeprom*/
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ret = fdtdec_setup_mem_size_base();
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if (ret)
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goto err;
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/*read memory size info*/
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ret = get_data_from_eeprom(offset, len, (u8 *)&data);
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if (ret == len)
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gd->ram_size = (phys_size_t)((hextoul((char *)&data, NULL) & 0xff) << 30);
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ret = 0;
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ret = get_data_from_eeprom(offset, len, &data);
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if (ret == len) {
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size = ((phys_size_t)hextoul(&data, NULL)) << 30;
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if (check_eeprom_dram_info(size))
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gd->ram_size = size;
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}
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ret = 0;
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err:
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return ret;
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}
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|
|
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|
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Starfive, Inc.
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* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
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* Author: yanhong <yanhong.wang@starfivetech.com>
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* samin <samin.guo@starfivetech.com>
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*/
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|
|
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|
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Starfive, Inc.
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* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
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* Author: yanhong <yanhong.wang@starfivetech.com>
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||||
*
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*/
|
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|
|
|
|||
|
|
@ -71,6 +71,16 @@
|
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};
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||||
};
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&cachectrl {
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reg = <0x0 0x2010000 0x0 0x4000>,
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<0x0 0x2030000 0x0 0x80000>,
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<0x0 0x8000000 0x0 0x2000000>;
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reg-names = "control", "prefetcher", "sideband";
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prefetch-dist-size = <0x4>;
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prefetch-hart-mask = <0x1e>;
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prefetch-enable;
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};
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&uart0 {
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clock-frequency = <24000000>;
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current-speed = <115200>;
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|
|
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|
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@ -20,7 +20,7 @@
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "sifive,u74-mc", "riscv";
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compatible = "sifive,s7", "riscv";
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reg = <0>;
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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|
|
@ -35,7 +35,7 @@
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i-tlb-size = <40>;
|
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mmu-type = "riscv,sv39";
|
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imacu";
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riscv,isa = "rv64imacu_zba_zbb";
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tlb-split;
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status = "disabled";
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|
|
@ -62,7 +62,7 @@
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux";
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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status = "okay";
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|
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|
|
@ -89,7 +89,7 @@
|
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux";
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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status = "okay";
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|
|
@ -116,7 +116,7 @@
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux";
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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status = "okay";
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|
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|
|
@ -143,7 +143,7 @@
|
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i-tlb-size = <40>;
|
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
|
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riscv,isa = "rv64imafdcbsux";
|
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riscv,isa = "rv64imafdcbsux_zba_zbb";
|
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tlb-split;
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status = "okay";
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|
|
@ -165,12 +165,9 @@
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|
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmcounters = <0x5 0x06 0x18
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0x08 0x09 0x18>;
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riscv,event-to-mhpmcounters = <0x5 0x06 0x18>;
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riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000
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0x06 0x00000000 0x4001
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0x08 0x00000000 0x4008
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0x09 0x00000000 0x4009>;
|
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0x06 0x00000000 0x4001>;
|
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riscv,raw-event-to-mhpmcounters =
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<0x00000000 0x100 0xffffffff 0xffffffff 0x18
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0x00000000 0x200 0xffffffff 0xffffffff 0x18
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|
|
@ -555,6 +552,7 @@
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reg-names = "control";
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interrupts = <91>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <64>;
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status = "okay";
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@ -566,6 +564,7 @@
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reg-names = "control";
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interrupts = <90>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <4>;
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status = "okay";
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|
|
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@ -314,7 +314,11 @@
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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rxc_dly_en = <1>;
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rgmii_sw_dr_2 = <0x0>;
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rgmii_sw_dr = <0x3>;
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rgmii_sw_dr_rxc = <0x6>;
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rxc_dly_en = <0>;
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rx_delay_sel = <0xa>;
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tx_delay_sel_fe = <5>;
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tx_delay_sel = <0xa>;
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tx_inverted_10 = <0x1>;
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@ -328,9 +332,13 @@
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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rgmii_sw_dr_2 = <0x0>;
|
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rgmii_sw_dr = <0x3>;
|
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rgmii_sw_dr_rxc = <0x6>;
|
||||
tx_delay_sel_fe = <5>;
|
||||
tx_delay_sel = <0>;
|
||||
rxc_dly_en = <0>;
|
||||
rx_delay_sel = <0x2>;
|
||||
tx_inverted_10 = <0x1>;
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||||
tx_inverted_100 = <0x1>;
|
||||
tx_inverted_1000 = <0x0>;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd.
|
||||
# Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
#
|
||||
|
||||
obj-y := starfive_evb.o
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
@ -27,12 +27,14 @@ enum chip_type_t {
|
|||
};
|
||||
|
||||
enum cpu_voltage_type_t {
|
||||
CPU_VOL_1020 = 0x0e,
|
||||
CPU_VOL_1040 = 0xff,
|
||||
CPU_VOL_1060 = 0xf0,
|
||||
CPU_VOL_1080 = 0xf1,
|
||||
CPU_VOL_1100 = 0xf2,
|
||||
CPU_VOL_1020 = 0xef0,
|
||||
CPU_VOL_1040 = 0xfff,
|
||||
CPU_VOL_1060 = 0xff0,
|
||||
CPU_VOL_1080 = 0xfe0,
|
||||
CPU_VOL_1100 = 0xf80,
|
||||
CPU_VOL_1120 = 0xf00,
|
||||
};
|
||||
#define CPU_VOL_MASK 0xfff
|
||||
|
||||
#define SYS_CLOCK_ENABLE(clk) \
|
||||
setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
|
||||
|
|
@ -212,8 +214,10 @@ static void get_cpu_voltage_type(struct udevice *dev)
|
|||
if (ret != sizeof(buf))
|
||||
printf("%s: error reading CPU vol from OTP\n", __func__);
|
||||
else {
|
||||
buf = 0x0e;
|
||||
switch ((buf & 0xff)) {
|
||||
switch ((buf & CPU_VOL_MASK)) {
|
||||
case CPU_VOL_1120:
|
||||
env_set("cpu_max_vol", "1120000");
|
||||
break;
|
||||
case CPU_VOL_1100:
|
||||
env_set("cpu_max_vol", "1100000");
|
||||
break;
|
||||
|
|
@ -234,32 +238,10 @@ static void get_cpu_voltage_type(struct udevice *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
/*enable U74-mc hart1~hart4 prefetcher*/
|
||||
static void enable_prefetcher(void)
|
||||
{
|
||||
u32 hart;
|
||||
u32 *reg;
|
||||
#define L2_PREFETCHER_BASE_ADDR 0x2030000
|
||||
#define L2_PREFETCHER_OFFSET 0x2000
|
||||
|
||||
/*hart1~hart4*/
|
||||
for (hart = 1; hart < 5; hart++) {
|
||||
reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR
|
||||
+ hart*L2_PREFETCHER_OFFSET));
|
||||
|
||||
mb(); /* memory barrier */
|
||||
setbits_le32(reg, 0x1);
|
||||
mb(); /* memory barrier */
|
||||
}
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
enable_caches();
|
||||
|
||||
/*enable hart1-hart4 prefetcher*/
|
||||
enable_prefetcher();
|
||||
|
||||
jh7110_timer_init();
|
||||
jh7110_usb_init(true);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd.
|
||||
# Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
#
|
||||
|
||||
obj-y := starfive_visionfive2.o
|
||||
|
|
|
|||
|
|
@ -53,12 +53,14 @@ enum board_type_t {
|
|||
|
||||
|
||||
enum cpu_voltage_type_t {
|
||||
CPU_VOL_1020 = 0x0e,
|
||||
CPU_VOL_1040 = 0xff,
|
||||
CPU_VOL_1060 = 0xf0,
|
||||
CPU_VOL_1080 = 0xf1,
|
||||
CPU_VOL_1100 = 0xf2,
|
||||
CPU_VOL_1020 = 0xef0,
|
||||
CPU_VOL_1040 = 0xfff,
|
||||
CPU_VOL_1060 = 0xff0,
|
||||
CPU_VOL_1080 = 0xfe0,
|
||||
CPU_VOL_1100 = 0xf80,
|
||||
CPU_VOL_1120 = 0xf00,
|
||||
};
|
||||
#define CPU_VOL_MASK 0xfff
|
||||
|
||||
static void sys_reset_clear(ulong assert, ulong status, u32 rst)
|
||||
{
|
||||
|
|
@ -311,7 +313,10 @@ static void get_cpu_voltage_type(struct udevice *dev)
|
|||
if (ret != sizeof(buf))
|
||||
printf("%s: error reading CPU vol from OTP\n", __func__);
|
||||
else {
|
||||
switch ((buf & 0xff)) {
|
||||
switch ((buf & CPU_VOL_MASK)) {
|
||||
case CPU_VOL_1120:
|
||||
env_set("cpu_max_vol", "1120000");
|
||||
break;
|
||||
case CPU_VOL_1100:
|
||||
env_set("cpu_max_vol", "1100000");
|
||||
break;
|
||||
|
|
@ -332,25 +337,6 @@ static void get_cpu_voltage_type(struct udevice *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
/*enable U74-mc hart1~hart4 prefetcher*/
|
||||
static void enable_prefetcher(void)
|
||||
{
|
||||
u32 hart;
|
||||
u32 *reg;
|
||||
#define L2_PREFETCHER_BASE_ADDR 0x2030000
|
||||
#define L2_PREFETCHER_OFFSET 0x2000
|
||||
|
||||
/*hart1~hart4*/
|
||||
for (hart = 1; hart < 5; hart++) {
|
||||
reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR
|
||||
+ hart*L2_PREFETCHER_OFFSET));
|
||||
|
||||
mb(); /* memory barrier */
|
||||
setbits_le32(reg, 0x1);
|
||||
mb(); /* memory barrier */
|
||||
}
|
||||
}
|
||||
|
||||
static void jh7110_jtag_init(void)
|
||||
{
|
||||
/*jtag*/
|
||||
|
|
@ -430,9 +416,6 @@ int board_init(void)
|
|||
{
|
||||
enable_caches();
|
||||
|
||||
/*enable hart1-hart4 prefetcher*/
|
||||
enable_prefetcher();
|
||||
|
||||
jh7110_jtag_init();
|
||||
jh7110_timer_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ CONFIG_ARCH_RV64I=y
|
|||
CONFIG_CMODEL_MEDANY=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_SHOW_REGS=y
|
||||
# CONFIG_OF_BOARD_FIXUP is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_FIT_SOURCE="jh7110-uboot-fit-image.its"
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
|
|
@ -27,7 +28,7 @@ CONFIG_SPI_BOOT=y
|
|||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=tty1 console=ttyS0,115200 debug rootwait earlycon=sbi "
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="fatload mmc 0:3 $kernel_addr_r jh7110_uEnv.txt; env import -t $kernel_addr_r $filesize;run boot2"
|
||||
CONFIG_BOOTCOMMAND="run mmcbootenv;run boot2"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="run chipa_set_uboot"
|
||||
CONFIG_LOG_MAX_LEVEL=4
|
||||
|
|
@ -37,6 +38,7 @@ CONFIG_DISPLAY_BOARDINFO=y
|
|||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
|
|
@ -58,7 +60,6 @@ CONFIG_CMD_SYSBOOT=y
|
|||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FS_UUID=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ CONFIG_SPI_BOOT=y
|
|||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=tty1 console=ttyS0,115200 debug rootwait earlycon=sbi"
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run load_vf2_env;run importbootenv;run boot2; run load_distro_uenv;run distro_bootcmd"
|
||||
CONFIG_BOOTCOMMAND="run load_vf2_env;run importbootenv;run boot2; run scan_boot_dev; run load_distro_uenv;run distro_bootcmd"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="run chipa_set_uboot;run mmcbootenv"
|
||||
CONFIG_DEFAULT_FDT_FILE="starfive/starfive_visionfive2.dtb"
|
||||
|
|
|
|||
93
drivers/cache/cache-sifive-ccache.c
vendored
93
drivers/cache/cache-sifive-ccache.c
vendored
|
|
@ -15,10 +15,96 @@
|
|||
|
||||
#define SIFIVE_CCACHE_WAY_ENABLE 0x008
|
||||
|
||||
|
||||
/* Prefetch */
|
||||
#define SIFIVE_PREFET_HARD_BASE(hart) ((hart)*0x2000)
|
||||
/* Prefetch Control Register */
|
||||
#define SIFIVE_PREFT_EN_MASK BIT(0)
|
||||
#define SIFIVE_PREFT_CROSS_PAGE_DIS_MASK BIT(1)
|
||||
#define SIFIVE_PREFT_DIST_MASK GENMASK(7, 2)
|
||||
#define SIFIVE_PREFT_MAX_ALLOC_DIST_MASK GENMASK(13, 8)
|
||||
#define SIFIVE_PREFT_LIN_TO_EXP_THRD_MASK GENMASK(19, 14)
|
||||
#define SIFIVE_PREFT_AGE_OUT_EN_MASK BIT(20)
|
||||
#define SIFIVE_PREFT_NUM_LDS_AGE_OUT_MASK GENMASK(27, 21)
|
||||
#define SIFIVE_PREFT_CROSS_PAGE_EN_MASK BIT(28)
|
||||
|
||||
/* Prefetch Advanced Control Register */
|
||||
#define SIFIVE_PREFT_ADV_Q_FULL_THRD GENMASK(3, 0)
|
||||
#define SIFIVE_PREFT_ADV_HIT_CACHE_THRD GENMASK(8, 4)
|
||||
#define SIFIVE_PREFT_ADV_HIT_MSHR_THRD GENMASK(12, 9)
|
||||
#define SIFIVE_PREFT_ADV_WINDOW_MASK GENMASK(18, 13)
|
||||
|
||||
#define SIFIVE_PREFET_HARD_MASK 0x1e
|
||||
#define SIFIVE_MAX_HART_ID 0x20
|
||||
#define SIFIVE_PREFT_DIST_VAL 0x3
|
||||
#define SIFIVE_PREFT_DIST_MAX 0x3f
|
||||
#define SIFIVE_PREFT_EN 0x1
|
||||
|
||||
struct sifive_ccache {
|
||||
void __iomem *base;
|
||||
void __iomem *pre_base;
|
||||
u32 pre_hart_mask;
|
||||
u32 pre_dist_size;
|
||||
};
|
||||
|
||||
static int sifive_prefetcher_parse(struct udevice *dev)
|
||||
{
|
||||
struct sifive_ccache *priv = dev_get_priv(dev);
|
||||
|
||||
if (!priv->pre_base)
|
||||
return -EINVAL;
|
||||
|
||||
if (!dev_read_bool(dev, "prefetch-enable"))
|
||||
return -ENOENT;
|
||||
|
||||
priv->pre_hart_mask = dev_read_u32_default(dev, "prefetch-hart-mask",
|
||||
SIFIVE_PREFET_HARD_MASK);
|
||||
priv->pre_dist_size = dev_read_u32_default(dev, "prefetch-dist-size",
|
||||
SIFIVE_PREFT_DIST_VAL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sifive_prefetcher_cfg_by_id(struct udevice *dev, u32 hart)
|
||||
{
|
||||
struct sifive_ccache *priv = dev_get_priv(dev);
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
|
||||
/* Prefetch Control Register */
|
||||
reg = priv->pre_base + SIFIVE_PREFET_HARD_BASE(hart);
|
||||
|
||||
val = readl(reg);
|
||||
val &= ~SIFIVE_PREFT_MAX_ALLOC_DIST_MASK;
|
||||
val |= SIFIVE_PREFT_DIST_MAX << __ffs(SIFIVE_PREFT_MAX_ALLOC_DIST_MASK);
|
||||
writel(val, reg);
|
||||
|
||||
val = readl(reg);
|
||||
val &= ~SIFIVE_PREFT_DIST_MASK;
|
||||
val |= priv->pre_dist_size << __ffs(SIFIVE_PREFT_DIST_MASK);
|
||||
writel(val, reg);
|
||||
|
||||
val |= SIFIVE_PREFT_EN << __ffs(SIFIVE_PREFT_EN_MASK);
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
static int sifive_prefetcher_enable(struct udevice *dev)
|
||||
{
|
||||
struct sifive_ccache *priv = dev_get_priv(dev);
|
||||
u32 hart;
|
||||
int ret;
|
||||
|
||||
ret = sifive_prefetcher_parse(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (hart = 0; hart < SIFIVE_MAX_HART_ID; hart++) {
|
||||
if (BIT(hart) & priv->pre_hart_mask)
|
||||
sifive_prefetcher_cfg_by_id(dev, hart);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sifive_ccache_enable(struct udevice *dev)
|
||||
{
|
||||
struct sifive_ccache *priv = dev_get_priv(dev);
|
||||
|
|
@ -31,6 +117,8 @@ static int sifive_ccache_enable(struct udevice *dev)
|
|||
|
||||
writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
|
||||
|
||||
sifive_prefetcher_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -51,11 +139,16 @@ static const struct cache_ops sifive_ccache_ops = {
|
|||
static int sifive_ccache_probe(struct udevice *dev)
|
||||
{
|
||||
struct sifive_ccache *priv = dev_get_priv(dev);
|
||||
fdt_addr_t addr;
|
||||
|
||||
priv->base = dev_read_addr_ptr(dev);
|
||||
if (!priv->base)
|
||||
return -EINVAL;
|
||||
|
||||
addr = dev_read_addr_name(dev, "prefetcher");
|
||||
if (addr != FDT_ADDR_T_NONE)
|
||||
priv->pre_base = (void *)(uintptr_t)addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
#define YTPHY_SPEED_MODE 0xc000
|
||||
#define YTPHY_SPEED_MODE_BIT 14
|
||||
#define YTPHY_RGMII_SW_DR_MASK GENMASK(5, 4)
|
||||
#define YTPHY_RGMII_RXC_DR_MASK GENMASK(15, 13)
|
||||
|
||||
#define YT8521_EXT_CLK_GATE 0xc
|
||||
#define YT8521_EN_SLEEP_SW_BIT 15
|
||||
|
|
@ -73,6 +74,12 @@ struct ytphy_reg_field {
|
|||
const u8 dflt; /* Default value */
|
||||
};
|
||||
|
||||
static const struct ytphy_reg_field ytphy_dr_grp[] = {
|
||||
{ "rgmii_sw_dr", 2, 4, 0x3},
|
||||
{ "rgmii_sw_dr_2", 1, 12, 0x0},
|
||||
{ "rgmii_sw_dr_rxc", 3, 13, 0x3}
|
||||
};
|
||||
|
||||
static const struct ytphy_reg_field ytphy_rxtxd_grp[] = {
|
||||
{ "rx_delay_sel", 4, 10, 0x0 },
|
||||
{ "tx_delay_sel_fe", 4, 4, 0xf },
|
||||
|
|
@ -228,9 +235,20 @@ static int ytphy_of_config(struct phy_device *phydev)
|
|||
ytphy_write_ext(phydev, YTPHY_EXTREG_CHIP_CONFIG, val);
|
||||
}
|
||||
|
||||
/* set drive strenght of rxd/rx_ctl rgmii pad */
|
||||
val = ytphy_read_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG);
|
||||
val |= YTPHY_RGMII_SW_DR_MASK;
|
||||
for (i = 0; i < ARRAY_SIZE(ytphy_dr_grp); i++) {
|
||||
|
||||
cfg = ofnode_read_u32_default(node,
|
||||
ytphy_dr_grp[i].name, ~0);
|
||||
cfg = (cfg != -1) ? cfg : ytphy_dr_grp[i].dflt;
|
||||
|
||||
/*check the cfg overflow or not*/
|
||||
cfg = (cfg > ((1 << ytphy_dr_grp[i].size) - 1)) ?
|
||||
((1 << ytphy_dr_grp[i].size) - 1) : cfg;
|
||||
|
||||
val = bitfield_replace(val, ytphy_dr_grp[i].off,
|
||||
ytphy_dr_grp[i].size, cfg);
|
||||
}
|
||||
ytphy_write_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG, val);
|
||||
|
||||
val = ytphy_read_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1);
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Pinctrl / GPIO driver for StarFive JH7100 SoC
|
||||
*
|
||||
* Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
|
||||
* Author: Jianlong Huang <jianlong.huang@starfivetech.com>
|
||||
*/
|
||||
|
|
@ -275,10 +275,25 @@ const struct pinctrl_ops starfive_pinctrl_ops = {
|
|||
.pinconf_set = starfive_pinconf_set,
|
||||
};
|
||||
|
||||
static int starfive_gpio_get_direction(struct udevice *dev, unsigned int off)
|
||||
{
|
||||
struct udevice *pdev = dev->parent;
|
||||
struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
|
||||
struct starfive_pinctrl_soc_info *info = priv->info;
|
||||
|
||||
unsigned int offset = 4 * (off / 4);
|
||||
unsigned int shift = 8 * (off % 4);
|
||||
u32 doen = readl(priv->base + info->doen_reg_base + offset);
|
||||
|
||||
doen = (doen >> shift) & info->doen_mask;
|
||||
|
||||
return doen == GPOEN_ENABLE ? GPIOF_OUTPUT : GPIOF_INPUT;
|
||||
}
|
||||
|
||||
static int starfive_gpio_direction_input(struct udevice *dev, unsigned int off)
|
||||
{
|
||||
struct udevice *pdev = dev->parent;
|
||||
struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
|
||||
struct starfive_pinctrl_soc_info *info = priv->info;
|
||||
|
||||
/* enable input and schmitt trigger */
|
||||
|
|
@ -297,7 +312,7 @@ static int starfive_gpio_direction_output(struct udevice *dev,
|
|||
unsigned int off, int val)
|
||||
{
|
||||
struct udevice *pdev = dev->parent;
|
||||
struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
|
||||
struct starfive_pinctrl_soc_info *info = priv->info;
|
||||
|
||||
if (info->set_one_pinmux)
|
||||
|
|
@ -365,6 +380,7 @@ static int starfive_gpio_probe(struct udevice *dev)
|
|||
}
|
||||
|
||||
static const struct dm_gpio_ops starfive_gpio_ops = {
|
||||
.get_function = starfive_gpio_get_direction,
|
||||
.direction_input = starfive_gpio_direction_input,
|
||||
.direction_output = starfive_gpio_direction_output,
|
||||
.get_value = starfive_gpio_get_value,
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Pinctrl / GPIO driver for StarFive SoC
|
||||
*
|
||||
* Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
|
||||
* Author: Jianlong Huang <jianlong.huang@starfivetech.com>
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: samin <samin.guo@starfivetech.com>
|
||||
* yanhong <yanhong.wang@starfivetech.com>
|
||||
*
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/**
|
||||
* cdns-starfive.c - Cadence USB Controller
|
||||
*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: yanhong <yanhong.wang@starfivetech.com>
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -120,20 +120,42 @@
|
|||
"cpu_vol_1100_set=" \
|
||||
"fdt set /opp-table-0/opp-1500000000 opp-microvolt <1100000>;\0"
|
||||
|
||||
#define CPU_VOL_1120_SET \
|
||||
"cpu_vol_1120_set=" \
|
||||
"fdt set /opp-table-0/opp-1500000000 opp-microvolt <1120000>;\0"
|
||||
|
||||
#define CPU_VOL_SET \
|
||||
"cpu_vol_set=" \
|
||||
"if test ${cpu_max_vol} = 1100000; then " \
|
||||
"run cpu_vol_1100_set;" \
|
||||
"elif test ${cpu_max_vol} = 1080000; then " \
|
||||
"run cpu_vol_1080_set;" \
|
||||
"elif test ${cpu_max_vol} = 1060000; then " \
|
||||
"run cpu_vol_1060_set;" \
|
||||
"elif test ${cpu_max_vol} = 1020000; then " \
|
||||
"run cpu_vol_1020_set;" \
|
||||
"else " \
|
||||
"run cpu_vol_1040_set;" \
|
||||
"cpu_vol_set=" \
|
||||
"if test ${cpu_max_vol} = 1120000; then " \
|
||||
"run cpu_vol_1120_set;" \
|
||||
"elif test ${cpu_max_vol} = 1100000; then " \
|
||||
"run cpu_vol_1100_set;" \
|
||||
"elif test ${cpu_max_vol} = 1080000; then " \
|
||||
"run cpu_vol_1080_set;" \
|
||||
"elif test ${cpu_max_vol} = 1060000; then " \
|
||||
"run cpu_vol_1060_set;" \
|
||||
"elif test ${cpu_max_vol} = 1020000; then " \
|
||||
"run cpu_vol_1020_set;" \
|
||||
"else " \
|
||||
"run cpu_vol_1040_set;" \
|
||||
"fi; \0"
|
||||
|
||||
#define EVB_BOOTENV_NVME \
|
||||
"sdev_cmd=mmc\0" \
|
||||
"sdev_blk=mmcblk0p4\0" \
|
||||
"scan_nvme_dev=" \
|
||||
"if pci enum; then " \
|
||||
"nvme scan; " \
|
||||
"echo pci enum ...;" \
|
||||
"fi; " \
|
||||
"if nvme dev; then " \
|
||||
"setenv sdev_cmd nvme;" \
|
||||
"setenv sdev_blk nvme0n1p4;" \
|
||||
"fi; \0" \
|
||||
"mmcbootenv=run scan_nvme_dev; " \
|
||||
"fatload ${sdev_cmd} 0:3 $kernel_addr_r jh7110_uEnv.txt; " \
|
||||
"env import -t $kernel_addr_r $filesize; \0"
|
||||
|
||||
#define CHIPA_GMAC_SET \
|
||||
"chipa_gmac_set=" \
|
||||
"fdt set /soc/ethernet@16030000/ethernet-phy@0 tx_inverted_10 <0x1>;" \
|
||||
|
|
@ -169,11 +191,13 @@
|
|||
"ramdisk_addr_r=0x46100000\0" \
|
||||
CHIPA_GMAC_SET \
|
||||
CHIPA_SET \
|
||||
EVB_BOOTENV_NVME \
|
||||
CPU_VOL_1020_SET \
|
||||
CPU_VOL_1040_SET \
|
||||
CPU_VOL_1060_SET \
|
||||
CPU_VOL_1080_SET \
|
||||
CPU_VOL_1100_SET \
|
||||
CPU_VOL_1120_SET \
|
||||
CPU_VOL_SET \
|
||||
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
|
||||
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
|
||||
|
|
|
|||
|
|
@ -118,9 +118,15 @@
|
|||
"cpu_vol_1100_set=" \
|
||||
"fdt set /opp-table-0/opp-1500000000 opp-microvolt <1100000>;\0"
|
||||
|
||||
#define CPU_VOL_1120_SET \
|
||||
"cpu_vol_1120_set=" \
|
||||
"fdt set /opp-table-0/opp-1500000000 opp-microvolt <1120000>;\0"
|
||||
|
||||
#define CPU_VOL_SET \
|
||||
"cpu_vol_set=" \
|
||||
"if test ${cpu_max_vol} = 1100000; then " \
|
||||
"cpu_vol_set=" \
|
||||
"if test ${cpu_max_vol} = 1120000; then " \
|
||||
"run cpu_vol_1120_set;" \
|
||||
"elif test ${cpu_max_vol} = 1100000; then " \
|
||||
"run cpu_vol_1100_set;" \
|
||||
"elif test ${cpu_max_vol} = 1080000; then " \
|
||||
"run cpu_vol_1080_set;" \
|
||||
|
|
@ -135,32 +141,52 @@
|
|||
#define VF2_DISTRO_BOOTENV \
|
||||
"fatbootpart=1:3\0" \
|
||||
"distroloadaddr=0xb0000000\0" \
|
||||
"load_distro_uenv=" \
|
||||
"fatload mmc ${devnum}:3 ${distroloadaddr} /${bootenv}; " \
|
||||
"bootdev=mmc\0" \
|
||||
"scan_boot_dev=" \
|
||||
"if test ${bootmode} = flash; then " \
|
||||
"if pci enum; then " \
|
||||
"nvme scan; " \
|
||||
"echo pci enum ...;" \
|
||||
"fi; " \
|
||||
"if nvme dev; then " \
|
||||
"setenv fatbootpart ${devnvme}:${nvmepart};" \
|
||||
"setenv devnum ${devnvme};" \
|
||||
"setenv bootdev nvme;" \
|
||||
"else " \
|
||||
"if mmc dev ${devnum}; then " \
|
||||
"echo found device ${devnum};" \
|
||||
"else " \
|
||||
"setenv devnum 0;" \
|
||||
"mmc dev 0;" \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; \0" \
|
||||
"load_distro_uenv=" \
|
||||
"fatload ${bootdev} ${devnum}:3 ${distroloadaddr} /${bootenv}; " \
|
||||
"setenv fatbootpart ${devnum}:3; " \
|
||||
"env import ${distroloadaddr} 200; \0" \
|
||||
"fdt_loaddtb=" \
|
||||
"fatload mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile}; fdt addr ${fdt_addr_r}; \0" \
|
||||
"fatload ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile}; fdt addr ${fdt_addr_r}; \0" \
|
||||
"fdt_sizecheck=" \
|
||||
"fatsize mmc ${fatbootpart} /dtbs/${fdtfile}; \0" \
|
||||
"fatsize ${bootdev} ${fatbootpart} /dtbs/${fdtfile}; \0" \
|
||||
"set_fdt_distro=" \
|
||||
"if test ${chip_vision} = A; then " \
|
||||
"if test ${memory_size} = 200000000; then " \
|
||||
"run chipa_gmac_set;" \
|
||||
"run visionfive2_mem_set;" \
|
||||
"fatwrite mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \
|
||||
"fatwrite ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \
|
||||
"else " \
|
||||
"run chipa_gmac_set;" \
|
||||
"run visionfive2_mem_set;" \
|
||||
"fatwrite mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \
|
||||
"fatwrite ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \
|
||||
"fi;" \
|
||||
"else " \
|
||||
"run visionfive2_mem_set;" \
|
||||
"run cpu_vol_set;" \
|
||||
"fatwrite mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \
|
||||
"fatwrite ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \
|
||||
"fi; \0" \
|
||||
"bootcmd_distro=" \
|
||||
"run fdt_loaddtb; run fdt_sizecheck; run set_fdt_distro; sysboot mmc ${fatbootpart} fat c0000000 /${boot_syslinux_conf}; \0" \
|
||||
"run fdt_loaddtb; run fdt_sizecheck; run set_fdt_distro; sysboot ${bootdev} ${fatbootpart} fat c0000000 /${boot_syslinux_conf}; \0" \
|
||||
|
||||
#define PARTS_DEFAULT \
|
||||
"name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
|
||||
|
|
@ -204,6 +230,11 @@
|
|||
"run visionfive2_mem_set;" \
|
||||
"run chipa_gmac_set; \0" \
|
||||
|
||||
#define VISIONFIVE2_BOOTENV_NVME \
|
||||
"nvmepart=3\0" \
|
||||
"devnvme=0\0" \
|
||||
"nvme_env=vf2_nvme_uEnv.txt\0" \
|
||||
|
||||
#define VISIONFIVE2_BOOTENV \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"testenv=vf2_uEnv.txt\0" \
|
||||
|
|
@ -215,41 +246,54 @@
|
|||
"ext4bootenv=" \
|
||||
"ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0"\
|
||||
"importbootenv=" \
|
||||
"echo Importing environment from mmc${devnum} ...; " \
|
||||
"echo Importing environment from ${devnum}/${devnvme} ...; "\
|
||||
"env import -t ${loadaddr} ${filesize}\0" \
|
||||
"scan_mmc_dev=" \
|
||||
"if test ${bootmode} = flash; then " \
|
||||
"if mmc dev ${devnum}; then " \
|
||||
"echo found device ${devnum};" \
|
||||
"else " \
|
||||
"setenv devnum 0;" \
|
||||
"mmc dev 0;" \
|
||||
"if pci enum; then " \
|
||||
"nvme scan; " \
|
||||
"echo pci enum ...;" \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"echo bootmode ${bootmode} device ${devnum};\0" \
|
||||
"if nvme dev; then " \
|
||||
"setenv btpart ${devnvme}:${nvmepart};" \
|
||||
"setenv load_vf2_env fatload nvme ${btpart} ${loadaddr} ${nvme_env};" \
|
||||
"else " \
|
||||
"if mmc dev ${devnum}; then " \
|
||||
"echo found device ${devnum};" \
|
||||
"else " \
|
||||
"setenv devnum 0;" \
|
||||
"mmc dev 0;" \
|
||||
"fi; " \
|
||||
"if mmc rescan; then " \
|
||||
"run loadbootenv && run importbootenv; "\
|
||||
"run ext4bootenv && run importbootenv; "\
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...; " \
|
||||
"run uenvcmd; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"echo bootmode ${bootmode} device ${devnum}/${devnvme};\0" \
|
||||
"mmcbootenv=run scan_mmc_dev; " \
|
||||
"setenv bootpart ${devnum}:${mmcpart}; " \
|
||||
"if mmc rescan; then " \
|
||||
"run loadbootenv && run importbootenv; " \
|
||||
"run ext4bootenv && run importbootenv; " \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...; " \
|
||||
"run uenvcmd; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"setenv bootpart ${devnum}:${mmcpart};\0" \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_addr_r=0x40200000\0" \
|
||||
"kernel_comp_addr_r=0x90000000\0" \
|
||||
"kernel_comp_size=0x10000000\0" \
|
||||
"fdt_addr_r=0x46000000\0" \
|
||||
"scriptaddr=0x43900000\0" \
|
||||
"script_offset_f=0x1fff000\0" \
|
||||
"script_size_f=0x1000\0" \
|
||||
"pxefile_addr_r=0x45900000\0" \
|
||||
"ramdisk_addr_r=0x46100000\0" \
|
||||
"fdtoverlay_addr_r=0x4f000000\0" \
|
||||
VF2_DISTRO_BOOTENV \
|
||||
VISIONFIVE2_BOOTENV_NVME \
|
||||
VISIONFIVE2_BOOTENV \
|
||||
CHIPA_GMAC_SET \
|
||||
CHIPA_SET \
|
||||
|
|
@ -258,6 +302,7 @@
|
|||
CPU_VOL_1060_SET \
|
||||
CPU_VOL_1080_SET \
|
||||
CPU_VOL_1100_SET \
|
||||
CPU_VOL_1120_SET \
|
||||
CPU_VOL_SET \
|
||||
CHIPA_SET_FORCE \
|
||||
VISIONFIVE2_MEM_SET \
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* Copyright 2022 StarFive, Inc <xingyu.wu@starfivetech.com>
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: XingYu Wu <xingyu.wu@starfivetech.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* Copyright 2022 StarFive, Inc <xingyu.wu@starfivetech.com>
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: XingYu Wu <xingyu.wu@starfivetech.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_ISP_H__
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* Copyright (C) 2022 Starfive, Inc.
|
||||
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
||||
* Author: samin <samin.guo@starfivetech.com>
|
||||
* yanhong <yanhong.wang@starfivetech.com>
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue