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Merge branch 'CR_3508_update_toolchain' into 'jh7110-master'
CR_3508: riscv: dts: starfive: add zicsr_zifencei to riscv,isa string See merge request sdk/u-boot!54
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commit
d64059f32b
1 changed files with 6 additions and 6 deletions
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@ -20,7 +20,7 @@
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "sifive,u74-mc", "riscv";
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compatible = "sifive,s7", "riscv";
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reg = <0>;
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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@ -35,7 +35,7 @@
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imacu";
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riscv,isa = "rv64imacu_zba_zbb";
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tlb-split;
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status = "disabled";
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@ -62,7 +62,7 @@
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux";
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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status = "okay";
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@ -89,7 +89,7 @@
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux";
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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status = "okay";
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@ -116,7 +116,7 @@
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux";
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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status = "okay";
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@ -143,7 +143,7 @@
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux";
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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status = "okay";
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