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Merge branch 'CR_3508_update_toolchain' into 'jh7110-master'

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CR_3508: riscv: dts: starfive: add zicsr_zifencei to riscv,isa string

See merge request sdk/u-boot!54
This commit is contained in:
andy.hu 2023-05-19 03:34:49 +00:00
commit d64059f32b
1 changed files with 6 additions and 6 deletions
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12
arch/riscv/dts/jh7110.dtsi
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@ -20,7 +20,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "sifive,u74-mc", "riscv";
compatible = "sifive,s7", "riscv";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
@ -35,7 +35,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imacu";
riscv,isa = "rv64imacu_zba_zbb";
tlb-split;
status = "disabled";
@ -62,7 +62,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdcbsux";
riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";
@ -89,7 +89,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdcbsux";
riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";
@ -116,7 +116,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdcbsux";
riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";
@ -143,7 +143,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdcbsux";
riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";