mirror of
https://github.com/Fishwaldo/u-boot.git
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Merge branch 'master' of git://git.denx.de/u-boot-imx
This commit is contained in:
commit
d75c2a3d7f
10 changed files with 80 additions and 116 deletions
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@ -43,14 +43,14 @@ void reset_cpu (ulong ignored)
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{
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struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
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/* Disable watchdog and set Time-Out field to 0 */
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writel (0x00000000, ®s->wcr);
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writew(0, ®s->wcr);
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/* Write Service Sequence */
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writel (0x00005555, ®s->wsr);
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writel (0x0000AAAA, ®s->wsr);
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writew(WSR_UNLOCK1, ®s->wsr);
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writew(WSR_UNLOCK2, ®s->wsr);
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/* Enable watchdog */
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writel (WCR_WDE, ®s->wcr);
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writew(WCR_WDE, ®s->wcr);
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while (1) ;
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}
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@ -269,7 +269,7 @@ u32 imx_get_fecclk(void)
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/*
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* Dump some core clockes.
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*/
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int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 freq;
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@ -1,73 +0,0 @@
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/*
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* January 2004 - Changed to support H4 device
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* Copyright (c) 2004 Texas Instruments
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN(4);
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.text :
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{
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arch/arm/cpu/armv7/start.o
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*(.text)
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}
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. = ALIGN(4);
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.rodata : { *(.rodata) }
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. = ALIGN(4);
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.data : {
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*(.data)
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__datarel_start = .;
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*(.data.rel)
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__datarelrolocal_start = .;
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*(.data.rel.ro.local)
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__datarellocal_start = .;
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*(.data.rel.local)
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__datarelro_start = .;
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*(.data.rel.ro)
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}
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__got_start = .;
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. = ALIGN(4);
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.got : { *(.got) }
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__got_end = .;
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = ALIGN(4);
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__bss_start = .;
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.bss : { *(.bss) }
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_end = .;
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}
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@ -108,11 +108,11 @@ struct gpt_regs {
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/* Watchdog Timer (WDOG) registers */
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struct wdog_regs {
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u32 wcr; /* Control */
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u32 wsr; /* Service */
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u32 wrsr; /* Reset Status */
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u32 wicr; /* Interrupt Control */
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u32 wmcr; /* Misc Control */
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u16 wcr; /* Control */
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u16 wsr; /* Service */
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u16 wrsr; /* Reset Status */
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u16 wicr; /* Interrupt Control */
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u16 wmcr; /* Misc Control */
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};
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/* IIM control registers */
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@ -308,7 +308,9 @@ struct iim_regs {
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#define GPT_CTRL_TEN 1 /* Timer enable */
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/* WDOG enable */
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#define WCR_WDE 0x04
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#define WCR_WDE 0x04
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#define WSR_UNLOCK1 0x5555
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#define WSR_UNLOCK2 0xAAAA
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/* FUSE bank offsets */
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#define IIM0_MAC 0x1a
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@ -26,7 +26,8 @@
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/*
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* IRAM
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*/
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#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
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#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
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#define IRAM_SIZE 0x00020000 /* 128 KB */
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/*
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* Graphics Memory of GPU
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*/
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@ -20,7 +20,6 @@
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# MA 02111-1307 USA
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#
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LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
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CONFIG_SYS_TEXT_BASE = 0x97800000
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IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
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ALL += $(obj)u-boot.imx
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@ -52,9 +52,9 @@ u32 get_board_rev(void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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@ -188,10 +188,10 @@ static void power_init(void)
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val &= ~PWGT2SPIEN;
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pmic_reg_write(REG_POWER_MISC, val);
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/* Write needed to update Charger 0 */
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pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
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ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
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OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
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/* Externally powered */
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val = pmic_reg_read(REG_CHARGE);
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val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
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pmic_reg_write(REG_CHARGE, val);
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/* power up the system first */
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pmic_reg_write(REG_POWER_MISC, PWUP);
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@ -20,6 +20,6 @@
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# MA 02111-1307 USA
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#
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LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
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TEXT_BASE = 0x97800000
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CONFIG_SYS_TEXT_BASE = 0x97800000
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IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
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ALL += $(obj)u-boot.imx
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@ -24,6 +24,7 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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@ -50,7 +51,6 @@
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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/* size in bytes reserved for initial data */
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#define BOARD_LATE_INIT
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@ -124,18 +124,42 @@
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#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot_addr=0xa0000000\0" \
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"uboot=u-boot.bin\0" \
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"loadaddr=0x90800000\0" \
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"bootargs_base=setenv bootargs console=tty "\
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"console=ttymxc0,${baudrate}\0"\
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"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_nfs; " \
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"tftpboot ${loadaddr} ${kernel}; bootm\0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"uimage=uImage\0" \
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"mmcdev=0\0" \
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"mmcpart=2\0" \
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"mmcroot=/dev/mmcblk0p3 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm\0" \
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"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"dhcp ${uimage}; bootm\0" \
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#define CONFIG_BOOTCOMMAND \
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"if mmc rescan ${mmcdev}; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else run netboot; fi"
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#define CONFIG_ARP_TIMEOUT 200UL
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@ -143,6 +167,8 @@
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > "
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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@ -173,6 +199,15 @@
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_DDR_CLKSEL 0
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#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
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@ -29,24 +29,24 @@
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/* REG_CHARGE */
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#define VCHRG0 0
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#define VCHRG0 (1 << 0)
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#define VCHRG1 (1 << 1)
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#define VCHRG2 (1 << 2)
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#define ICHRG0 (1 << 3)
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#define ICHRG1 (1 << 4)
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#define ICHRG2 (1 << 5)
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#define ICHRG3 (1 << 6)
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#define ICHRGTR0 (1 << 7)
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#define ICHRGTR1 (1 << 8)
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#define ICHRGTR2 (1 << 9)
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#define TREN (1 << 7)
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#define ACKLPB (1 << 8)
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#define THCHKB (1 << 9)
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#define FETOVRD (1 << 10)
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#define FETCTRL (1 << 11)
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#define RVRSMODE (1 << 13)
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#define OVCTRL0 (1 << 15)
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#define OVCTRL1 (1 << 16)
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#define UCHEN (1 << 17)
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#define PLIM0 (1 << 15)
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#define PLIM1 (1 << 16)
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#define PLIMDIS (1 << 17)
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#define CHRGLEDEN (1 << 18)
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#define CHRGRAWPDEN (1 << 19)
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#define CHGTMRRST (1 << 19)
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#define CHGRESTART (1 << 20)
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#define CHGAUTOB (1 << 21)
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#define CYCLB (1 << 22)
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