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Merge branch '2021-10-03-platform-updates' into next

Browse source 
- TI K3 updates, add IOT2050 platform
- rtc rx8025 updates, PCI fixes
This commit is contained in:
Tom Rini 2021-10-03 19:31:04 -04:00
commit e17cbdd050
61 changed files with 4053 additions and 723 deletions
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9
arch/arm/dts/Makefile
View file

@ -1090,7 +1090,14 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_AM6) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
k3-am65-iot2050-spl.dtb \
k3-am6528-iot2050-basic.dtb \
k3-am6528-iot2050-basic-pg2.dtb \
k3-am6548-iot2050-advanced.dtb \
k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \

4
arch/arm/dts/ast2600.dtsi
View file

@ -474,21 +474,25 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785000 0x40>;
status = "disabled";
};
wdt2: watchdog@1e785040 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785040 0x40>;
status = "disabled";
};
wdt3: watchdog@1e785080 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785080 0x40>;
status = "disabled";
};
wdt4: watchdog@1e7850C0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";
};
lpc: lpc@1e789000 {

447
arch/arm/dts/k3-am64-main.dtsi
View file

@ -5,6 +5,17 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>
/ {
serdes_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
@ -26,6 +37,20 @@
};
};
main_conf: syscon@43000000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x0 0x43000000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x43000000 0x20000>;
serdes_ln_ctrl: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@ -50,12 +75,12 @@
};
};
dmss: dmss {
dmss: bus@48000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges;
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
ti,sci-dev-id = <25>;
@ -142,7 +167,7 @@
};
};
dmsc: dmsc@44043000 {
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@ -156,7 +181,7 @@
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
@ -197,8 +222,6 @@
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -210,8 +233,6 @@
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -223,8 +244,6 @@
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -236,8 +255,6 @@
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -249,8 +266,6 @@
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -262,8 +277,6 @@
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -275,8 +288,6 @@
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -381,6 +392,52 @@
clocks = <&k3_clks 145 0>;
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <3>;
ti,interrupt-ranges = <0 32 16>;
};
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <190>, <191>, <192>,
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <87>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
};
main_gpio1: gpio@601000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <88>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
clock-names = "gpio";
};
sdhci0: mmc@fa10000 {
compatible = "ti,am64-sdhci-8bit";
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
@ -451,7 +508,8 @@
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 de ad be ef];
mac-address = [00 00 00 00 00 00];
ti,syscon-efuse = <&main_conf 0x200>;
};
cpsw_port2: port@2 {
@ -459,7 +517,7 @@
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 01 de ad be ef];
mac-address = [00 00 00 00 00 00];
};
};
@ -485,30 +543,23 @@
};
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
<77 1 IRQ_TYPE_EDGE_RISING>,
<77 2 IRQ_TYPE_EDGE_RISING>,
<77 3 IRQ_TYPE_EDGE_RISING>,
<77 4 IRQ_TYPE_EDGE_RISING>,
<77 5 IRQ_TYPE_EDGE_RISING>,
<77 6 IRQ_TYPE_EDGE_RISING>,
<77 7 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
cpts@39000000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x39000000 0x0 0x400>;
reg-names = "cpts";
power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 84 0>;
clock-names = "cpts";
assigned-clocks = <&k3_clks 84 0>;
assigned-clock-parents = <&k3_clks 84 8>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
};
usbss0: cdns-usb@f900000{
compatible = "ti,am64-usb", "ti,j721e-usb";
compatible = "ti,am64-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
@ -537,69 +588,275 @@
};
};
main_gpio1: gpio@601000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00601000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
<78 1 IRQ_TYPE_EDGE_RISING>,
<78 2 IRQ_TYPE_EDGE_RISING>,
<78 3 IRQ_TYPE_EDGE_RISING>,
<78 4 IRQ_TYPE_EDGE_RISING>,
<78 5 IRQ_TYPE_EDGE_RISING>,
<78 6 IRQ_TYPE_EDGE_RISING>,
<78 7 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
clock-names = "gpio";
tscadc0: tscadc@28001000 {
compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
reg = <0x00 0x28001000 0x00 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 0 0>;
assigned-clocks = <&k3_clks 0 0>;
assigned-clock-parents = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck";
adc {
#io-channel-cells = <1>;
compatible = "ti,am654-adc", "ti,am3359-adc";
};
};
main_i2c0: i2c@20000000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x0 0x20000000 0x0 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 102 2>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
fss: bus@fc00000 {
compatible = "simple-bus";
reg = <0x00 0x0fc00000 0x00 0x70000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ospi0: spi@fc40000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <&k3_clks 75 6>;
assigned-clocks = <&k3_clks 75 6>;
assigned-clock-parents = <&k3_clks 75 7>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
};
};
main_i2c1: i2c@20010000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x0 0x20010000 0x0 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 103 2>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
hwspinlock: spinlock@2a000000 {
compatible = "ti,am64-hwspinlock";
reg = <0x00 0x2a000000 0x00 0x1000>;
#hwlock-cells = <1>;
};
main_i2c2: i2c@20020000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20020000 0x0 0x100>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 104 2>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
mailbox0_cluster2: mailbox@29020000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29020000 0x00 0x200>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
main_i2c3: i2c@20030000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20030000 0x0 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
mailbox0_cluster3: mailbox@29030000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29030000 0x00 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster4: mailbox@29040000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29040000 0x00 0x200>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster5: mailbox@29050000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29050000 0x00 0x200>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster6: mailbox@29060000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29060000 0x00 0x200>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster7: mailbox@29070000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29070000 0x00 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
main_r5fss0: r5fss@78000000 {
compatible = "ti,am64-r5fss";
ti,cluster-mode = <0>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0x78000000 0x00 0x78000000 0x10000>,
<0x78100000 0x00 0x78100000 0x10000>,
<0x78200000 0x00 0x78200000 0x08000>,
<0x78300000 0x00 0x78300000 0x08000>;
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@78000000 {
compatible = "ti,am64-r5f";
reg = <0x78000000 0x00010000>,
<0x78100000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <121>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 121 1>;
firmware-name = "am64-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@78200000 {
compatible = "ti,am64-r5f";
reg = <0x78200000 0x00008000>,
<0x78300000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <122>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 122 1>;
firmware-name = "am64-main-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss1: r5fss@78400000 {
compatible = "ti,am64-r5fss";
ti,cluster-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x78400000 0x00 0x78400000 0x10000>,
<0x78500000 0x00 0x78500000 0x10000>,
<0x78600000 0x00 0x78600000 0x08000>,
<0x78700000 0x00 0x78700000 0x08000>;
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
main_r5fss1_core0: r5f@78400000 {
compatible = "ti,am64-r5f";
reg = <0x78400000 0x00010000>,
<0x78500000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <123>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 123 1>;
firmware-name = "am64-main-r5f1_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss1_core1: r5f@78600000 {
compatible = "ti,am64-r5f";
reg = <0x78600000 0x00008000>,
<0x78700000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <124>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 124 1>;
firmware-name = "am64-main-r5f1_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
serdes_wiz0: wiz@f000000 {
compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
num-lanes = <1>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
assigned-clocks = <&k3_clks 162 1>;
assigned-clock-parents = <&k3_clks 162 5>;
serdes0: serdes@f000000 {
compatible = "ti,j721e-serdes-10g";
reg = <0x0f000000 0x00010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 162 1>,
<&k3_clks 162 1>,
<&k3_clks 162 1>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
};
};
pcie0_rc: pcie@f102000 {
compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x68000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
max-link-speed = <2>;
num-lanes = <1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
cdns,no-bar-match-nbits = <64>;
vendor-id = <0x104c>;
device-id = <0xb010>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
};
pcie0_ep: pcie-ep@f102000 {
compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x68000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
max-link-speed = <2>;
num-lanes = <1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fck";
clocks = <&k3_clks 105 2>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
max-functions = /bits/ 8 <1>;
};
};

32
arch/arm/dts/k3-am64-mcu.dtsi
View file

@ -9,8 +9,6 @@
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -22,8 +20,6 @@
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -73,4 +69,32 @@
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
};
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <5>;
ti,interrupt-ranges = <0 104 4>;
};
mcu_gpio0: gpio@4201000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x4201000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&mcu_gpio_intr>;
interrupts = <30>, <31>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <23>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
};
};

2
arch/arm/dts/k3-am64.dtsi
View file

@ -28,8 +28,6 @@
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};

259
arch/arm/dts/k3-am642-evm.dts
View file

@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
@ -36,6 +38,60 @@
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
evm_12v0: fixedregulator-evm12v0 {
@ -154,6 +210,15 @@
>;
};
main_spi0_pins_default: main-spi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@ -207,6 +272,22 @@
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
ospi0_pins_default: ospi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
};
&main_uart0 {
@ -285,6 +366,11 @@
};
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_i2c0 {
status = "disabled";
};
@ -301,28 +387,16 @@
status = "disabled";
};
&cpsw3g {
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
pinctrl-0 = <&main_spi0_pins_default>;
ti,pindir-d0-out-d1-in;
eeprom@0 {
compatible = "microchip,93lc46b";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
spi-max-frequency = <1000000>;
spi-cs-high;
data-size = <16>;
};
};
@ -355,3 +429,148 @@
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "reserved";
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&mailbox0_cluster2 {
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&pcie0_rc {
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&pcie0_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};

299
arch/arm/dts/k3-am642-sk.dts
View file

@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
@ -35,6 +37,93 @@
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
vusb_main: fixed-regulator-vusb-main5v0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
/* output of LP8733xx */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vusb_main>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vcc_3v3_sys>;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
};
@ -52,6 +141,12 @@
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@ -99,6 +194,30 @@
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
ospi0_pins_default: ospi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
};
&mcu_uart0 {
status = "disabled";
};
&mcu_uart1 {
status = "disabled";
};
&main_uart1 {
@ -126,8 +245,51 @@
status = "disabled";
};
&mcu_i2c0 {
status = "disabled";
};
&mcu_i2c1 {
status = "disabled";
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"PRU_DETECT", "MMC1_SD_EN",
"VPP_LDO_EN", "RPI_PS_3V3_En",
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
};
};
&main_i2c3 {
status = "disabled";
};
&mcu_spi0 {
status = "disabled";
};
&mcu_spi1 {
status = "disabled";
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
@ -135,6 +297,33 @@
disable-wp;
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_USB>;
};
&serdes0 {
serdes0_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 1>;
};
};
&usbss0 {
ti,vbus-divider;
};
&usb0 {
dr_mode = "host";
maximum-speed = "super-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
@ -147,10 +336,120 @@
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
status = "disabled";
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&mailbox0_cluster2 {
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&pcie0_rc {
status = "disabled";
};
&pcie0_ep {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2020-2021
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
* Chao Zeng <chao.zeng@siemens.com>
*/
#include <config.h>
/ {
binman {
filename = "flash.bin";
pad-byte = <0xff>;
size = <0x8c0000>;
blob-ext@0x000000 {
offset = <0x000000>;
filename = "tiboot3.bin";
};
blob@0x080000 {
offset = <0x080000>;
filename = "tispl.bin";
};
fit@0x280000 {
description = "U-Boot for IOT2050";
offset = <0x280000>;
images {
u-boot {
description = "U-Boot";
type = "standalone";
arch = "arm64";
os = "u-boot";
compression = "none";
load = <0x80800000>;
entry = <0x80800000>;
u-boot-nodtb {
};
};
fdt-iot2050-basic {
description = "k3-am6528-iot2050-basic.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6528-iot2050-basic.dtb";
};
};
fdt-iot2050-basic-pg2 {
description = "k3-am6528-iot2050-basic-pg2.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6528-iot2050-basic-pg2.dtb";
};
};
fdt-iot2050-advanced {
description = "k3-am6548-iot2050-advanced.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6548-iot2050-advanced.dtb";
};
};
fdt-iot2050-advanced-pg2 {
description = "k3-am6548-iot2050-advanced-pg2.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dtb";
};
};
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
k3-rti-wdt-firmware {
type = "firmware";
load = <0x82000000>;
arch = "arm";
compression = "none";
blob-ext {
filename = CONFIG_WDT_K3_RTI_FW_FILE;
missing-msg = "k3-rti-wdt-firmware";
};
};
#endif
};
configurations {
default = "conf-iot2050-basic";
conf-iot2050-basic {
description = "iot2050-basic";
firmware = "u-boot";
fdt = "fdt-iot2050-basic";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
conf-iot2050-basic-pg2 {
description = "iot2050-basic-pg2";
firmware = "u-boot";
fdt = "fdt-iot2050-basic-pg2";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
conf-iot2050-advanced {
description = "iot2050-advanced";
firmware = "u-boot";
fdt = "fdt-iot2050-advanced";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
conf-iot2050-advanced-pg2 {
description = "iot2050-advanced-pg2";
firmware = "u-boot";
fdt = "fdt-iot2050-advanced-pg2";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
};
};
/* primary env */
fill@0x680000 {
offset = <0x680000>;
size = <0x020000>;
fill-byte = [00];
};
/* secondary env */
fill@0x6a0000 {
offset = <0x6a0000>;
size = <0x020000>;
fill-byte = [00];
};
/* PG1 sysfw, basic variant */
blob-ext@0x6c0000 {
offset = <0x6c0000>;
filename = "sysfw.itb";
};
/* PG1 sysfw, advanced variant */
blob-ext@0x740000 {
offset = <0x740000>;
filename = "sysfw.itb_HS";
};
/* PG2 sysfw, basic variant */
blob-ext@0x7c0000 {
offset = <0x7c0000>;
filename = "sysfw_sr2.itb";
};
/* PG2 sysfw, advanced variant */
blob-ext@0x840000 {
offset = <0x840000>;
filename = "sysfw_sr2.itb_HS";
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2021
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common bits of the IOT2050 Basic and Advanced variants, PG1
*/
&dss {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
};
&serdes0 {
status = "disabled";
};
&sdhci1 {
no-1-8-v;
};
&tx_pru0_0 {
status = "disabled";
};
&tx_pru0_1 {
status = "disabled";
};
&tx_pru1_0 {
status = "disabled";
};
&tx_pru1_1 {
status = "disabled";
};
&tx_pru2_0 {
status = "disabled";
};
&tx_pru2_1 {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2021
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common bits of the IOT2050 Basic and Advanced variants, PG2
*/
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-pin-default {
pinctrl-single,pins = <
/* (AF12) GPIO1_24, used as cp2102 reset */
AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
>;
};
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&cp2102n_reset_pin_default>;
gpio-line-names =
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "CP2102N-RESET";
};
&dss {
/* Workaround needed to get DP clock of 154Mhz */
assigned-clocks = <&k3_clks 67 0>;
};
&serdes0 {
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
};
&dwc3_0 {
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
phys = <&serdes0 PHY_TYPE_USB3 0>;
phy-names = "usb3-phy";
};
&usb0_phy {
maximum-speed = "super-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common U-Boot bits of the IOT2050 Basic and Advanced variants
*/
/ {
aliases {
spi0 = &ospi0;
};
leds {
u-boot,dm-spl;
status-led-red {
u-boot,dm-spl;
};
status-led-green {
u-boot,dm-spl;
};
};
};
&cbass_mcu {
u-boot,dm-spl;
};
&cbass_wakeup {
u-boot,dm-spl;
};
&cbass_main {
u-boot,dm-spl;
main-navss {
u-boot,dm-spl;
};
};
&wkup_pmx0 {
u-boot,dm-spl;
mcu-fss0-ospi0-pins-default {
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main-uart1-pins-default {
u-boot,dm-spl;
};
};
&main_uart1 {
u-boot,dm-spl;
current-speed = <115200>;
};
&wkup_gpio0 {
u-boot,dm-spl;
};
&ospi0 {
u-boot,dm-spl;
flash@0 {
u-boot,dm-spl;
};
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
u-boot,dm-spl;
};
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&fss {
u-boot,dm-spl;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
*/
#include "k3-am654.dtsi"
#include <dt-bindings/phy/phy.h>
/ {
aliases {
spi0 = &mcu_spi0;
mmc0 = &sdhci1;
mmc1 = &sdhci0;
};
chosen {
stdout-path = "serial3:115200n8";
bootargs = "earlycon=ns16550a,mmio32,0x02810000";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: secure-ddr@9e800000 {
reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0 0xa0000000 0 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0 0xa0100000 0 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0 0xa1000000 0 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0 0xa1100000 0 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a2000000 {
reg = <0x00 0xa2000000 0x00 0x00200000>;
alignment = <0x1000>;
no-map;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
status-led-red {
gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
status-led-green {
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
};
user-led1-red {
gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
};
user-led1-green {
gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
};
user-led2-red {
gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
};
user-led2-green {
gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
};
};
dp_refclk: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
/* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
/* (AD6) WKUP_I2C0_SDA */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0)
>;
};
mcu_i2c0_pins_default: mcu-i2c0-pins-default {
pinctrl-single,pins = <
/* (AD8) MCU_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
/* (AD7) MCU_I2C0_SDA */
AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0)
>;
};
arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
pinctrl-single,pins = <
/* (R2) WKUP_GPIO0_21 */
AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
>;
};
push_button_pins_default: push-button-pins-default {
pinctrl-single,pins = <
/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
>;
};
arduino_uart_pins_default: arduino-uart-pins-default {
pinctrl-single,pins = <
/* (P4) MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
/* (P5) MCU_UART0_TXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
>;
};
arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
pinctrl-single,pins = <
/* (P1) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
/* (N3) WKUP_GPIO0_33 */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
>;
};
arduino_io_oe_pins_default: arduino-io-oe-pins-default {
pinctrl-single,pins = <
/* (N4) WKUP_GPIO0_34 */
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
/* (M2) WKUP_GPIO0_36 */
AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
/* (M3) WKUP_GPIO0_37 */
AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
/* (M4) WKUP_GPIO0_38 */
AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
/* (M1) WKUP_GPIO0_41 */
AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
/* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
/* (U2) MCU_OSPI0_DQS */
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)
/* (U4) MCU_OSPI0_D0 */
AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)
/* (U5) MCU_OSPI0_D1 */
AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)
/* (R4) MCU_OSPI0_CSn0 */
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0)
>;
};
db9_com_mode_pins_default: db9-com-mode-pins-default {
pinctrl-single,pins = <
/* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
/* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */
AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)
/* (AC1) WKUP_GPIO0_7, used as uart0 term */
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)
/* (AC2) WKUP_GPIO0_6, used as uart0 en */
AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)
>;
};
leds_pins_default: leds-pins-default {
pinctrl-single,pins = <
/* (T2) WKUP_GPIO0_17, used as user led1 red */
AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
/* (R3) WKUP_GPIO0_22, used as user led1 green */
AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)
/* (R5) WKUP_GPIO0_24, used as status led red */
AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)
/* (N2) WKUP_GPIO0_32, used as status led green */
AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)
>;
};
mcu_spi0_pins_default: mcu-spi0-pins-default {
pinctrl-single,pins = <
/* (Y1) MCU_SPI0_CLK */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
/* (Y3) MCU_SPI0_D0 */
AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
/* (Y2) MCU_SPI0_D1 */
AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
/* (Y4) MCU_SPI0_CS0 */
AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
>;
};
minipcie_pins_default: minipcie-pins-default {
pinctrl-single,pins = <
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
>;
};
};
&main_pmx0 {
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */
AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */
>;
};
usb0_pins_default: usb0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
};
usb1_pins_default: usb1-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
};
arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */
AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */
>;
};
dss_vout1_pins_default: dss-vout1-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */
AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */
AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */
AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */
AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */
AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */
AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */
AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */
AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */
AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */
AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */
AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */
AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */
AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */
AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */
AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */
AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */
AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */
AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */
AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */
AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */
AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */
AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */
AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */
AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */
AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */
>;
};
dp_pins_default: dp-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
>;
};
};
&main_pmx1 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
ecap0_pins_default: ecap0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
};
};
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
};
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_uart2 {
status = "disabled";
};
&mcu_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&arduino_uart_pins_default>;
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
gpio-line-names =
"main_gpio0-base", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "IO4", "", "IO5", "", "", "IO6", "",
"", "", "", "IO7", "", "", "", "", "IO8", "",
"", "IO9";
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <
&arduino_io_d2_to_d3_pins_default
&arduino_i2c_aio_switch_pins_default
&arduino_io_oe_pins_default
&push_button_pins_default
&db9_com_mode_pins_default
>;
gpio-line-names =
/* 0..9 */
"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
"UART0-enable", "UART0-terminate", "", "WIFI-disable",
/* 10..19 */
"", "", "", "", "", "", "", "", "", "",
/* 20..29 */
"", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
/* 30..39 */
"IO1", "IO2", "", "IO3", "IO17-direction", "A5",
"IO16-direction", "IO15-direction", "IO14-direction", "A3",
/* 40..49 */
"", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
"IO11",
/* 50..51 */
"IO12", "IO10";
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
&mcu_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
psu: regulator@60 {
compatible = "ti,tps62363";
reg = <0x60>;
regulator-name = "tps62363-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
ti,enable-vout-discharge;
};
/* D4200 */
pcal9535_1: gpio@20 {
compatible = "nxp,pcal9535";
reg = <0x20>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names =
"A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
"A5-pull", "", "",
"IO14-enable", "IO15-enable", "IO16-enable",
"IO17-enable", "IO18-enable", "IO19-enable";
};
/* D4201 */
pcal9535_2: gpio@21 {
compatible = "nxp,pcal9535";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names =
"IO0-direction", "IO1-direction", "IO2-direction",
"IO3-direction", "IO4-direction", "IO5-direction",
"IO6-direction", "IO7-direction",
"IO8-direction", "IO9-direction", "IO10-direction",
"IO11-direction", "IO12-direction", "IO13-direction",
"IO19-direction";
};
/* D4202 */
pcal9535_3: gpio@25 {
compatible = "nxp,pcal9535";
reg = <0x25>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names =
"IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
"IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
"IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
"IO12-pull", "IO13-pull";
};
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
rtc: rtc8564@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
eeprom: eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
pagesize = <16>;
};
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&main_i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
edp-bridge@f {
compatible = "toshiba,tc358767";
reg = <0x0f>;
pinctrl-names = "default";
pinctrl-0 = <&dp_pins_default>;
reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
clock-names = "ref";
clocks = <&dp_refclk>;
toshiba,hpd-pin = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
bridge_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
};
};
};
&mcu_cpsw {
status = "disabled";
};
&ecap0 {
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "host";
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins_default>;
dr_mode = "host";
};
&mcu_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_spi0_pins_default>;
#address-cells = <1>;
#size-cells= <0>;
ti,pindir-d0-out-d1-in;
};
&tscadc0 {
status = "disabled";
};
&tscadc1 {
adc {
ti,adc-channels = <0 1 2 3 4 5>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <50000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&dss {
pinctrl-names = "default";
pinctrl-0 = <&dss_vout1_pins_default>;
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
};
&dss_ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dpi_out: endpoint {
remote-endpoint = <&bridge_in>;
};
};
};
&pcie0_rc {
status = "disabled";
};
&pcie0_ep {
status = "disabled";
};
&pcie1_rc {
pinctrl-names = "default";
pinctrl-0 = <&minipcie_pins_default>;
num-lanes = <1>;
phys = <&serdes1 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy0";
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
status = "disabled";
};
&mailbox0_cluster0 {
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-tx = <1 0 0>;
ti,mbox-rx = <0 0 0>;
};
};
&mailbox0_cluster1 {
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-tx = <1 0 0>;
ti,mbox-rx = <0 0 0>;
};
};
&mailbox0_cluster2 {
status = "disabled";
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
status = "disabled";
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "disabled";
};
&mailbox0_cluster7 {
status = "disabled";
};
&mailbox0_cluster8 {
status = "disabled";
};
&mailbox0_cluster9 {
status = "disabled";
};
&mailbox0_cluster10 {
status = "disabled";
};
&mailbox0_cluster11 {
status = "disabled";
};
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "disabled";
};
&icssg2_mdio {
status = "disabled";
};

17
arch/arm/dts/k3-am65-iot2050-spl.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
*/
/dts-v1/;
#include "k3-am65-iot2050-common.dtsi"
#include "k3-am65-iot2050-common-u-boot.dtsi"
/ {
compatible = "siemens,iot2050", "ti,am654";
model = "Siemens IOT2050";
};

74
arch/arm/dts/k3-am65-main.dtsi
View file

@ -84,8 +84,6 @@
main_uart0: serial@2800000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -95,8 +93,6 @@
main_uart1: serial@2810000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
@ -105,8 +101,6 @@
main_uart2: serial@2820000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
@ -256,7 +250,7 @@
#size-cells = <0>;
};
sdhci0: sdhci@4f80000 {
sdhci0: mmc@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
@ -271,21 +265,16 @@
ti,otap-del-sel-sdr12 = <0x0>;
ti,otap-del-sel-sdr25 = <0x0>;
ti,otap-del-sel-sdr50 = <0x8>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-sdr104 = <0x7>;
ti,otap-del-sel-ddr50 = <0x5>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x5>;
ti,otap-del-sel-hs400 = <0x0>;
ti,itap-del-sel-legacy = <0xa>;
ti,itap-del-sel-mmc-hs = <0x1>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
};
sdhci1: sdhci@4fa0000 {
sdhci1: mmc@4fa0000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
@ -302,11 +291,8 @@
ti,otap-del-sel-ddr50 = <0x4>;
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
ti,itap-del-sel-legacy = <0xa>;
ti,itap-del-sel-mmc-hs = <0x1>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
@ -440,8 +426,9 @@
#phy-cells = <0>;
};
intr_main_gpio: interrupt-controller0 {
intr_main_gpio: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x0 0x00a00000 0x0 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -451,18 +438,19 @@
ti,interrupt-ranges = <0 392 32>;
};
main-navss {
main_navss: bus@30800000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <118>;
intr_main_navss: interrupt-controller1 {
intr_main_navss: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x0 0x310e0000 0x0 0x2000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -714,6 +702,7 @@
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
};
pcie0_ep: pcie-ep@5500000 {
@ -746,6 +735,7 @@
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
device_type = "pci";
};
pcie1_ep: pcie-ep@5600000 {
@ -974,18 +964,6 @@
};
};
icssg0_iep0: iep@2e000 {
compatible = "ti,am654-icss-iep";
reg = <0x2e000 0x1000>;
clocks = <&icssg0_iepclk_mux>;
};
icssg0_iep1: iep@2f000 {
compatible = "ti,am654-icss-iep";
reg = <0x2f000 0x1000>;
clocks = <&icssg0_iepclk_mux>;
};
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@ -1077,7 +1055,6 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
@ -1128,18 +1105,6 @@
};
};
icssg1_iep0: iep@2e000 {
compatible = "ti,am654-icss-iep";
reg = <0x2e000 0x1000>;
clocks = <&icssg1_iepclk_mux>;
};
icssg1_iep1: iep@2f000 {
compatible = "ti,am654-icss-iep";
reg = <0x2f000 0x1000>;
clocks = <&icssg1_iepclk_mux>;
};
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@ -1231,7 +1196,6 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
@ -1282,18 +1246,6 @@
};
};
icssg2_iep0: iep@2e000 {
compatible = "ti,am654-icss-iep";
reg = <0x2e000 0x1000>;
clocks = <&icssg2_iepclk_mux>;
};
icssg2_iep1: iep@2f000 {
compatible = "ti,am654-icss-iep";
reg = <0x2f000 0x1000>;
clocks = <&icssg2_iepclk_mux>;
};
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@ -1385,8 +1337,6 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
};

15
arch/arm/dts/k3-am65-mcu.dtsi
View file

@ -23,8 +23,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
@ -116,11 +114,11 @@
};
};
mcu-navss {
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
@ -308,4 +306,13 @@
ti,loczrama = <1>;
};
};
mcu_rti1: watchdog@40610000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x40610000 0x0 0x100>;
clocks = <&k3_clks 135 0>;
power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
assigned-clocks = <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 135 4>;
};
};

15
arch/arm/dts/k3-am65-wakeup.dtsi
View file

@ -6,24 +6,24 @@
*/
&cbass_wakeup {
dmsc: dmsc {
dmsc: system-controller@44083000 {
compatible = "ti,am654-sci";
ti,host-id = <12>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
@ -50,8 +50,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,am654-uart";
reg = <0x42300000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -69,8 +67,9 @@
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
intr_wkup_gpio: interrupt-controller2 {
intr_wkup_gpio: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x42200000 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;

2
arch/arm/dts/k3-am65.dtsi
View file

@ -56,7 +56,7 @@
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

63
arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi Normal file
View file

@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common bits of the IOT2050 Basic variant, PG1 and PG2
*/
#include "k3-am65-iot2050-common.dtsi"
#include "k3-am65-iot2050-common-u-boot.dtsi"
#include "k3-am65-iot2050-boot-image.dtsi"
/ {
memory@80000000 {
device_type = "memory";
/* 1G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
};
cpus {
cpu-map {
/delete-node/ cluster1;
};
/delete-node/ cpu@100;
/delete-node/ cpu@101;
};
/delete-node/ l2-cache1;
};
/* eMMC */
&sdhci0 {
status = "disabled";
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */
AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */
AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */
AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
>;
};
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
&mcu_r5fss0 {
/* lock-step mode not supported on Basic boards */
ti,cluster-mode = <0>;
};

24
arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2
* 1 GB RAM, no eMMC, main_uart0 on connector X30
*
* Product homepage:
* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
/dts-v1/;
#include "k3-am6528-iot2050-basic-common.dtsi"
#include "k3-am65-iot2050-common-pg2.dtsi"
/ {
compatible = "siemens,iot2050-basic-pg2", "ti,am654";
model = "SIMATIC IOT2050 Basic PG2";
};

24
arch/arm/dts/k3-am6528-iot2050-basic.dts Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1
* 1 GB RAM, no eMMC, main_uart0 on connector X30
*
* Product homepage:
* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
/dts-v1/;
#include "k3-am6528-iot2050-basic-common.dtsi"
#include "k3-am65-iot2050-common-pg1.dtsi"
/ {
compatible = "siemens,iot2050-basic", "ti,am654";
model = "SIMATIC IOT2050 Basic";
};

81
arch/arm/dts/k3-am654-base-board.dts
View file

@ -86,10 +86,36 @@
};
};
clk_ov5640_fixed: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
evm_12v0: fixedregulator-evm12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vcc3v3_io: fixedregulator-vcc3v3io {
/* Output of TPS54334 */
compatible = "regulator-fixed";
regulator-name = "vcc3v3_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&evm_12v0>;
};
vdd_mmc1_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vcc3v3_io>;
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
};
};
@ -142,7 +168,7 @@
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
>;
};
@ -287,23 +313,6 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2_phy0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&main_i2c2 {
@ -322,7 +331,7 @@
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
#size-cells= <0>;
ti,pindir-d0-out-d1-in = <1>;
ti,pindir-d0-out-d1-in;
flash@0{
compatible = "jedec,spi-nor";
@ -350,10 +359,10 @@
* disable sdhci1
*/
&sdhci1 {
vmmc-supply = <&vdd_mmc1_sd>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
sdhci-caps-mask = <0x7 0x0>;
disable-wp;
};
@ -484,9 +493,9 @@
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <40000000>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
@ -497,14 +506,6 @@
};
};
&csi2_0 {
csi2_phy0: endpoint {
remote-endpoint = <&csi2_cam0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
@ -538,3 +539,15 @@
&dss {
status = "disabled";
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "disabled";
};
&icssg2_mdio {
status = "disabled";
};

4
arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
View file

@ -23,7 +23,7 @@
&cbass_main{
u-boot,dm-spl;
main-navss {
main_navss: bus@30800000 {
u-boot,dm-spl;
};
};
@ -31,7 +31,7 @@
&cbass_mcu {
u-boot,dm-spl;
mcu-navss {
mcu_navss: bus@28380000 {
u-boot,dm-spl;
ringacc@2b800000 {

59
arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi Normal file
View file

@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common bits of the IOT2050 Advanced variant, PG1 and PG2
*/
/dts-v1/;
#include "k3-am65-iot2050-common.dtsi"
#include "k3-am65-iot2050-common-u-boot.dtsi"
#include "k3-am65-iot2050-boot-image.dtsi"
/ {
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
};
&main_pmx0 {
main_mmc0_pins_default: main-mmc0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */
AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
};
};
/* eMMC */
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_uart0 {
status = "disabled";
};

29
arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts Normal file
View file

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2
* 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
*
* Product homepage:
* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
/dts-v1/;
#include "k3-am6548-iot2050-advanced-common.dtsi"
#include "k3-am65-iot2050-common-pg2.dtsi"
/ {
compatible = "siemens,iot2050-advanced-pg2", "ti,am654";
model = "SIMATIC IOT2050 Advanced PG2";
};
&mcu_r5fss0 {
/* lock-step mode not supported on this board */
ti,cluster-mode = <0>;
};

24
arch/arm/dts/k3-am6548-iot2050-advanced.dts Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1
* 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
*
* Product homepage:
* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
/dts-v1/;
#include "k3-am6548-iot2050-advanced-common.dtsi"
#include "k3-am65-iot2050-common-pg1.dtsi"
/ {
compatible = "siemens,iot2050-advanced", "ti,am654";
model = "SIMATIC IOT2050 Advanced";
};

10
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
View file

@ -41,7 +41,7 @@
u-boot,dm-spl;
};
mcu-navss{
mcu_navss: bus@28380000 {
u-boot,dm-spl;
#address-cells = <2>;
#size-cells = <2>;
@ -118,10 +118,6 @@
u-boot,dm-spl;
};
&wkup_i2c0_pins_default {
u-boot,dm-spl;
};
&wkup_i2c0 {
u-boot,dm-spl;
};
@ -165,10 +161,6 @@
u-boot,dm-spl;
};
&wkup_gpio_pins_default {
u-boot,dm-spl;
};
&mcu_fss0_hpb0_pins_default {
u-boot,dm-spl;
};

108
arch/arm/dts/k3-j7200-common-proc-board.dts
View file

@ -17,51 +17,67 @@
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
aliases {
remoteproc0 = &mcu_r5fss0_core0;
remoteproc1 = &mcu_r5fss0_core1;
remoteproc2 = &main_r5fss0_core0;
remoteproc3 = &main_r5fss0_core1;
evm_12v0: fixedregulator-evm12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixedregulator-sd {
/* Output of TPS22918 */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
};
vdd_sd_dv: gpio-regulator-vdd-sd-dv {
vdd_sd_dv: gpio-regulator-TLV71033 {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "vdd_sd_dv";
regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vsys_5v0>;
gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0
3300000 0x1>;
states = <1800000 0x0>,
<3300000 0x1>;
};
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
};
wkup_gpio_pins_default: wkup-gpio-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
@ -74,7 +90,7 @@
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
@ -115,17 +131,17 @@
>;
};
vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
>;
};
main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
>;
};
};
&wkup_uart0 {
@ -178,6 +194,22 @@
status = "disabled";
};
&main_gpio2 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
};
&wkup_gpio1 {
status = "disabled";
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
@ -288,7 +320,7 @@
};
&serdes0 {
serdes0_pcie_link: link@0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@ -296,7 +328,7 @@
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
serdes0_qsgmii_link: link@1 {
serdes0_qsgmii_link: phy@1 {
reg = <2>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@ -304,3 +336,17 @@
resets = <&serdes_wiz0 3>;
};
};
&pcie1_rc {
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
&pcie1_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
status = "disabled";
};

265
arch/arm/dts/k3-j7200-main.dtsi
View file

@ -2,7 +2,7 @@
/*
* Device Tree Source for J7200 SoC Family Main Domain peripherals
*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
@ -68,8 +68,9 @@
};
};
main_gpio_intr: interrupt-controller0 {
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -85,9 +86,12 @@
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <199>;
dma-coherent;
dma-ranges;
main_navss_intr: interrupt-controller1 {
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x00 0x310e0000 0x00 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -297,8 +301,6 @@
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -310,8 +312,6 @@
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -323,8 +323,6 @@
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -336,8 +334,6 @@
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -349,8 +345,6 @@
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -362,8 +356,6 @@
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -375,8 +367,6 @@
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -388,8 +378,6 @@
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -401,8 +389,6 @@
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -414,8 +400,6 @@
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -424,53 +408,6 @@
clock-names = "fclk";
};
main_sdhci0: sdhci@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x8>;
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
dma-coherent;
};
main_sdhci1: sdhci@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
};
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x2000000 0x00 0x100>;
@ -548,26 +485,51 @@
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
<105 1 IRQ_TYPE_EDGE_RISING>,
<105 2 IRQ_TYPE_EDGE_RISING>,
<105 3 IRQ_TYPE_EDGE_RISING>,
<105 4 IRQ_TYPE_EDGE_RISING>,
<105 5 IRQ_TYPE_EDGE_RISING>,
<105 6 IRQ_TYPE_EDGE_RISING>,
<105 7 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 0>;
clock-names = "gpio";
main_sdhci0: mmc@4f80000 {
compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_ahb", "clk_xin";
clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x8>;
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
};
main_sdhci1: mmc@4fb0000 {
compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_ahb", "clk_xin";
clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
};
serdes_wiz0: wiz@5060000 {
@ -626,6 +588,54 @@
};
};
pcie1_rc: pcie@2910000 {
compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 6>;
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
cdns,no-bar-match-nbits = <64>;
vendor-id = /bits/ 16 <0x104c>;
device-id = /bits/ 16 <0xb00f>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
pcie1_ep: pcie-ep@2910000 {
compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 6>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
dma-coherent;
};
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
@ -653,12 +663,81 @@
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
cdns,phyrst-a-enable;
};
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <145>, <146>, <147>, <148>,
<149>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 0>;
clock-names = "gpio";
};
main_gpio2: gpio@610000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00610000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <154>, <155>, <156>, <157>,
<158>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 0>;
clock-names = "gpio";
};
main_gpio4: gpio@620000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00620000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <163>, <164>, <165>, <166>,
<167>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 109 0>;
clock-names = "gpio";
};
main_gpio6: gpio@630000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00630000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <172>, <173>, <174>, <175>,
<176>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j7200-r5fss";
ti,cluster-mode = <0>;
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
@ -672,7 +751,7 @@
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <245>;
ti,sci-proc-ids = <0x06 0xFF>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 245 1>;
firmware-name = "j7200-main-r5f0_0-fw";
ti,atcm-enable = <1>;
@ -687,7 +766,7 @@
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <246>;
ti,sci-proc-ids = <0x07 0xFF>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 246 1>;
firmware-name = "j7200-main-r5f0_1-fw";
ti,atcm-enable = <1>;

62
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
View file

@ -2,11 +2,11 @@
/*
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
dmsc: dmsc@44083000 {
dmsc: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
@ -23,7 +23,7 @@
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
@ -73,8 +73,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -86,8 +84,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
@ -96,8 +92,9 @@
clock-names = "fclk";
};
wkup_gpio_intr: interrupt-controller2 {
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -107,6 +104,38 @@
ti,interrupt-ranges = <16 960 16>;
};
wkup_gpio0: gpio@42110000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42110000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&wkup_gpio_intr>;
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <85>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
};
wkup_gpio1: gpio@42100000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42100000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&wkup_gpio_intr>;
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <85>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
@ -269,6 +298,23 @@
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
};
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 103 0>;
assigned-clocks = <&k3_clks 103 0>;
assigned-clock-parents = <&k3_clks 103 2>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
};
tscadc0: tscadc@40200000 {

116
arch/arm/dts/k3-j7200-som-p0.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@ -25,6 +25,60 @@
alignment = <0x1000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a4000000 {
reg = <0x00 0xa4000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
};
@ -46,6 +100,22 @@
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
>;
};
};
&main_pmx0 {
@ -141,6 +211,30 @@
status = "disabled";
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
@ -157,3 +251,23 @@
"GPIO_LIN_EN", "CAN_STB";
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
#address-cells = <1>;
#size-cells = <1>;
};
};

2
arch/arm/dts/k3-j7200.dtsi
View file

@ -114,7 +114,7 @@
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

4
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
View file

@ -34,7 +34,7 @@
&cbass_main{
u-boot,dm-spl;
main-navss {
main_navss: bus@30000000 {
u-boot,dm-spl;
};
};
@ -50,7 +50,7 @@
u-boot,dm-spl;
};
mcu-navss {
mcu_navss: bus@28380000 {
u-boot,dm-spl;
ringacc@2b800000 {

62
arch/arm/dts/k3-j721e-common-proc-board.dts
View file

@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
/ {
chosen {
@ -237,7 +238,7 @@
J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
@ -358,7 +359,7 @@
};
&serdes3 {
serdes3_usb_link: link@0 {
serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@ -635,8 +636,45 @@
status = "disabled";
};
&cmn_refclk1 {
clock-frequency = <100000000>;
};
&wiz0_pll1_refclk {
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&cmn_refclk1>;
};
&wiz0_refclk_dig {
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&cmn_refclk1>;
};
&wiz1_pll1_refclk {
assigned-clocks = <&wiz1_pll1_refclk>;
assigned-clock-parents = <&cmn_refclk1>;
};
&wiz1_refclk_dig {
assigned-clocks = <&wiz1_refclk_dig>;
assigned-clock-parents = <&cmn_refclk1>;
};
&wiz2_pll1_refclk {
assigned-clocks = <&wiz2_pll1_refclk>;
assigned-clock-parents = <&cmn_refclk1>;
};
&wiz2_refclk_dig {
assigned-clocks = <&wiz2_refclk_dig>;
assigned-clock-parents = <&cmn_refclk1>;
};
&serdes0 {
serdes0_pcie_link: link@0 {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@ -646,7 +684,10 @@
};
&serdes1 {
serdes1_pcie_link: link@0 {
assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz1_pll1_refclk>;
serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@ -656,7 +697,10 @@
};
&serdes2 {
serdes2_pcie_link: link@0 {
assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz2_pll1_refclk>;
serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@ -718,3 +762,11 @@
&dss {
status = "disabled";
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "disabled";
};

474
arch/arm/dts/k3-j721e-main.dtsi
View file

@ -8,6 +8,20 @@
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
/ {
cmn_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
cmn_refclk1: clock-cmnrefclk1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@ -28,38 +42,6 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
pcie0_ctrl: syscon@4070 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00004070 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x4070 0x4070 0x4>;
};
pcie1_ctrl: syscon@4074 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00004074 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x4074 0x4074 0x4>;
};
pcie2_ctrl: syscon@4078 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00004078 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x4078 0x4078 0x4>;
};
pcie3_ctrl: syscon@407c {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x0000407c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x407c 0x407c 0x4>;
};
serdes_ln_ctrl: mux@4080 {
compatible = "mmio-mux";
reg = <0x00004080 0x50>;
@ -108,8 +90,9 @@
};
};
main_gpio_intr: interrupt-controller0 {
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -119,18 +102,19 @@
ti,interrupt-ranges = <8 392 56>;
};
main-navss {
main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <199>;
main_navss_intr: interrupt-controller1 {
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x0 0x310e0000 0x0 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -368,24 +352,12 @@
pinctrl-single,function-mask = <0xffffffff>;
};
dummy_cmn_refclk: dummy-cmn-refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
dummy_cmn_refclk1: dummy-cmn-refclk1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
@ -394,21 +366,21 @@
ranges = <0x5000000 0x0 0x5000000 0x10000>;
wiz0_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
@ -430,10 +402,13 @@
reg = <0x5000000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
<&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
"pll0_refclk", "pll1_refclk";
};
};
@ -442,7 +417,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
@ -451,21 +426,21 @@
ranges = <0x5010000 0x0 0x5010000 0x10000>;
wiz1_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 293 13>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll0_refclk>;
assigned-clock-parents = <&k3_clks 293 13>;
};
wiz1_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll1_refclk>;
assigned-clock-parents = <&k3_clks 293 0>;
};
wiz1_refclk_dig: refclk-dig {
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_refclk_dig>;
assigned-clock-parents = <&k3_clks 293 13>;
@ -487,10 +462,13 @@
reg = <0x5010000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
resets = <&serdes_wiz1 0>;
reset-names = "sierra_reset";
clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
<&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
"pll0_refclk", "pll1_refclk";
};
};
@ -499,7 +477,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
@ -508,21 +486,21 @@
ranges = <0x5020000 0x0 0x5020000 0x10000>;
wiz2_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 294 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll0_refclk>;
assigned-clock-parents = <&k3_clks 294 11>;
};
wiz2_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll1_refclk>;
assigned-clock-parents = <&k3_clks 294 0>;
};
wiz2_refclk_dig: refclk-dig {
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_refclk_dig>;
assigned-clock-parents = <&k3_clks 294 11>;
@ -544,10 +522,13 @@
reg = <0x5020000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
resets = <&serdes_wiz2 0>;
reset-names = "sierra_reset";
clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
<&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
"pll0_refclk", "pll1_refclk";
};
};
@ -556,7 +537,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
@ -565,21 +546,21 @@
ranges = <0x5030000 0x0 0x5030000 0x10000>;
wiz3_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 295 9>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 9>;
};
wiz3_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll1_refclk>;
assigned-clock-parents = <&k3_clks 295 0>;
};
wiz3_refclk_dig: refclk-dig {
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_refclk_dig>;
assigned-clock-parents = <&k3_clks 295 9>;
@ -601,10 +582,13 @@
reg = <0x5030000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
resets = <&serdes_wiz3 0>;
reset-names = "sierra_reset";
clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
<&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
"pll0_refclk", "pll1_refclk";
};
};
@ -618,7 +602,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
@ -645,13 +629,12 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@ -667,7 +650,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
@ -694,13 +677,12 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@ -716,7 +698,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
@ -743,13 +725,12 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 241 1>;
clock-names = "fck";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@ -765,7 +746,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
@ -792,13 +773,12 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 242 1>;
clock-names = "fck";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@ -809,8 +789,6 @@
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -822,8 +800,6 @@
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -835,8 +811,6 @@
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -848,8 +822,6 @@
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -861,8 +833,6 @@
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -874,8 +844,6 @@
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -887,8 +855,6 @@
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -900,8 +866,6 @@
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -913,8 +877,6 @@
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -926,8 +888,6 @@
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -1068,13 +1028,13 @@
clock-names = "gpio";
};
main_sdhci0: sdhci@4f80000 {
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
clock-names = "clk_ahb", "clk_xin";
clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
assigned-clocks = <&k3_clks 91 1>;
assigned-clock-parents = <&k3_clks 91 2>;
bus-width = <8>;
@ -1084,24 +1044,26 @@
ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
ti,otap-del-sel-hs400 = <0x0>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
ti,trm-icp = <0x8>;
ti,strobe-sel = <0x77>;
dma-coherent;
};
main_sdhci1: sdhci@4fb0000 {
main_sdhci1: mmc@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
clock-names = "clk_ahb", "clk_xin";
clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sd-hs = <0xf>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
@ -1117,17 +1079,17 @@
sdhci-caps-mask = <0x2 0x0>;
};
main_sdhci2: sdhci@4f98000 {
main_sdhci2: mmc@4f98000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
clock-names = "clk_ahb", "clk_xin";
clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
assigned-clocks = <&k3_clks 93 0>;
assigned-clock-parents = <&k3_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sd-hs = <0xf>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
@ -1696,4 +1658,286 @@
resets = <&k3_reset 15 1>;
firmware-name = "j7-c71_0-fw";
};
icssg0: icssg@b000000 {
compatible = "ti,j721e-icssg";
reg = <0x00 0xb000000 0x00 0x80000>;
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x0b000000 0x100000>;
icssg0_mem: memories@0 {
reg = <0x0 0x2000>,
<0x2000 0x2000>,
<0x10000 0x10000>;
reg-names = "dram0", "dram1",
"shrdram2";
};
icssg0_cfg: cfg@26000 {
compatible = "ti,pruss-cfg", "syscon";
reg = <0x26000 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x26000 0x2000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
icssg0_coreclk_mux: coreclk-mux@3c {
reg = <0x3c>;
#clock-cells = <0>;
clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
<&k3_clks 119 1>; /* icssg0_iclk */
assigned-clocks = <&icssg0_coreclk_mux>;
assigned-clock-parents = <&k3_clks 119 1>;
};
icssg0_iepclk_mux: iepclk-mux@30 {
reg = <0x30>;
#clock-cells = <0>;
clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
<&icssg0_coreclk_mux>; /* core_clk */
assigned-clocks = <&icssg0_iepclk_mux>;
assigned-clock-parents = <&icssg0_coreclk_mux>;
};
};
};
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
};
icssg0_mii_g_rt: mii-g-rt@33000 {
compatible = "ti,pruss-mii-g", "syscon";
reg = <0x33000 0x1000>;
};
icssg0_intc: interrupt-controller@20000 {
compatible = "ti,icssg-intc";
reg = <0x20000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host_intr0", "host_intr1",
"host_intr2", "host_intr3",
"host_intr4", "host_intr5",
"host_intr6", "host_intr7";
};
pru0_0: pru@34000 {
compatible = "ti,j721e-pru";
reg = <0x34000 0x3000>,
<0x22000 0x100>,
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-pru0_0-fw";
};
rtu0_0: rtu@4000 {
compatible = "ti,j721e-rtu";
reg = <0x4000 0x2000>,
<0x23000 0x100>,
<0x23400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-rtu0_0-fw";
};
tx_pru0_0: txpru@a000 {
compatible = "ti,j721e-tx-pru";
reg = <0xa000 0x1800>,
<0x25000 0x100>,
<0x25400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru0_0-fw";
};
pru0_1: pru@38000 {
compatible = "ti,j721e-pru";
reg = <0x38000 0x3000>,
<0x24000 0x100>,
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-pru0_1-fw";
};
rtu0_1: rtu@6000 {
compatible = "ti,j721e-rtu";
reg = <0x6000 0x2000>,
<0x23800 0x100>,
<0x23c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-rtu0_1-fw";
};
tx_pru0_1: txpru@c000 {
compatible = "ti,j721e-tx-pru";
reg = <0xc000 0x1800>,
<0x25800 0x100>,
<0x25c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru0_1-fw";
};
icssg0_mdio: mdio@32400 {
compatible = "ti,davinci_mdio";
reg = <0x32400 0x100>;
clocks = <&k3_clks 119 1>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
};
};
icssg1: icssg@b100000 {
compatible = "ti,j721e-icssg";
reg = <0x00 0xb100000 0x00 0x80000>;
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x0b100000 0x100000>;
icssg1_mem: memories@b100000 {
reg = <0x0 0x2000>,
<0x2000 0x2000>,
<0x10000 0x10000>;
reg-names = "dram0", "dram1",
"shrdram2";
};
icssg1_cfg: cfg@26000 {
compatible = "ti,pruss-cfg", "syscon";
reg = <0x26000 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x26000 0x2000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
icssg1_coreclk_mux: coreclk-mux@3c {
reg = <0x3c>;
#clock-cells = <0>;
clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
<&k3_clks 120 4>; /* icssg1_iclk */
assigned-clocks = <&icssg1_coreclk_mux>;
assigned-clock-parents = <&k3_clks 120 4>;
};
icssg1_iepclk_mux: iepclk-mux@30 {
reg = <0x30>;
#clock-cells = <0>;
clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
<&icssg1_coreclk_mux>; /* core_clk */
assigned-clocks = <&icssg1_iepclk_mux>;
assigned-clock-parents = <&icssg1_coreclk_mux>;
};
};
};
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
};
icssg1_mii_g_rt: mii-g-rt@33000 {
compatible = "ti,pruss-mii-g", "syscon";
reg = <0x33000 0x1000>;
};
icssg1_intc: interrupt-controller@20000 {
compatible = "ti,icssg-intc";
reg = <0x20000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host_intr0", "host_intr1",
"host_intr2", "host_intr3",
"host_intr4", "host_intr5",
"host_intr6", "host_intr7";
};
pru1_0: pru@34000 {
compatible = "ti,j721e-pru";
reg = <0x34000 0x4000>,
<0x22000 0x100>,
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-pru1_0-fw";
};
rtu1_0: rtu@4000 {
compatible = "ti,j721e-rtu";
reg = <0x4000 0x2000>,
<0x23000 0x100>,
<0x23400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-rtu1_0-fw";
};
tx_pru1_0: txpru@a000 {
compatible = "ti,j721e-tx-pru";
reg = <0xa000 0x1800>,
<0x25000 0x100>,
<0x25400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru1_0-fw";
};
pru1_1: pru@38000 {
compatible = "ti,j721e-pru";
reg = <0x38000 0x4000>,
<0x24000 0x100>,
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-pru1_1-fw";
};
rtu1_1: rtu@6000 {
compatible = "ti,j721e-rtu";
reg = <0x6000 0x2000>,
<0x23800 0x100>,
<0x23c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-rtu1_1-fw";
};
tx_pru1_1: txpru@c000 {
compatible = "ti,j721e-tx-pru";
reg = <0xc000 0x1800>,
<0x25800 0x100>,
<0x25c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru1_1-fw";
};
icssg1_mdio: mdio@32400 {
compatible = "ti,davinci_mdio";
reg = <0x32400 0x100>;
clocks = <&k3_clks 120 4>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
};
};
};

37
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
View file

@ -6,7 +6,7 @@
*/
&cbass_mcu_wakeup {
dmsc: dmsc@44083000 {
dmsc: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
@ -23,7 +23,7 @@
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
@ -73,8 +73,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -86,8 +84,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
@ -96,8 +92,9 @@
clock-names = "fclk";
};
wkup_gpio_intr: interrupt-controller2 {
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
@ -179,26 +176,8 @@
#size-cells = <2>;
ranges;
hbmc_mux: hbmc-mux {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
reg = <0x0 0x47034000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
assigned-clocks = <&k3_clks 102 0>;
assigned-clock-rates = <250000000>;
};
ospi0: spi@47040000 {
compatible = "ti,am654-ospi";
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
@ -215,7 +194,7 @@
};
ospi1: spi@47050000 {
compatible = "ti,am654-ospi";
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47050000 0x0 0x100>,
<0x7 0x00000000 0x1 0x00000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
@ -267,11 +246,11 @@
};
};
mcu-navss {
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;

36
arch/arm/dts/k3-j721e-som-p0.dtsi
View file

@ -150,25 +150,6 @@
>;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@ -186,19 +167,6 @@
};
};
&hbmc {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x0 0x0 0x4000000>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
@ -206,9 +174,9 @@
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <40000000>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;

3
arch/arm/dts/k3-j721e.dtsi
View file

@ -115,7 +115,7 @@
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a72-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
@ -126,7 +126,6 @@
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */

1
arch/arm/mach-k3/Kconfig
View file

@ -168,4 +168,5 @@ config K3_DM_FW
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
endif

32
board/siemens/iot2050/Kconfig Normal file
View file

@ -0,0 +1,32 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) Siemens AG, 2018-2021
#
# Authors:
# Le Jin <le.jin@siemens.com>
# Jan Kiszka <jan.kiszka@siemens.com>
config TARGET_IOT2050_A53
bool "IOT2050 running on A53"
select ARM64
select SOC_K3_AM6
select BOARD_LATE_INIT
select SYS_DISABLE_DCACHE_OPS
select BINMAN
if TARGET_IOT2050_A53
config SYS_BOARD
default "iot2050"
config SYS_VENDOR
default "siemens"
config SYS_CONFIG_NAME
default "iot2050"
config IOT2050_BOOT_SWITCH
bool "Disable eMMC boot via USER button (Advanced version only)"
default y
endif

9
board/siemens/iot2050/MAINTAINERS Normal file
View file

@ -0,0 +1,9 @@
IOT2050 BOARD
M: Le Jin <le.jin@siemens.com>
M: Jan Kiszka <jan.kiszka@siemens.com>
S: Maintained
F: board/siemens/iot2050/
F: include/configs/iot2050.h
F: configs/iot2050_defconfig
F: arch/arm/dts/iot2050-*
F: doc/board/siemens/iot2050.rst

10
board/siemens/iot2050/Makefile Normal file
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@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Makefile for Siemens IOT2050 board
# Copyright (c) Siemens AG, 2018-2021
#
# Authors:
# Le Jin <le.jin@siemens.com>
#
obj-y += board.o

272
board/siemens/iot2050/board.c Normal file
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@ -0,0 +1,272 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board specific initialization for IOT2050
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*/
#include <common.h>
#include <bootstage.h>
#include <dm.h>
#include <i2c.h>
#include <led.h>
#include <malloc.h>
#include <net.h>
#include <phy.h>
#include <spl.h>
#include <version.h>
#include <linux/delay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/gpio.h>
#include <asm/io.h>
#define IOT2050_INFO_MAGIC 0x20502050
struct iot2050_info {
u32 magic;
u16 size;
char name[20 + 1];
char serial[16 + 1];
char mlfb[18 + 1];
char uuid[32 + 1];
char a5e[18 + 1];
u8 mac_addr_cnt;
u8 mac_addr[8][ARP_HLEN];
char seboot_version[40 + 1];
} __packed;
/*
* Scratch SRAM (available before DDR RAM) contains extracted EEPROM data.
*/
#define IOT2050_INFO_DATA ((struct iot2050_info *) \
TI_SRAM_SCRATCH_BOARD_EEPROM_START)
DECLARE_GLOBAL_DATA_PTR;
static bool board_is_advanced(void)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
return info->magic == IOT2050_INFO_MAGIC &&
strstr((char *)info->name, "IOT2050-ADVANCED") != NULL;
}
static bool board_is_sr1(void)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
return info->magic == IOT2050_INFO_MAGIC &&
!strstr((char *)info->name, "-PG2");
}
static void remove_mmc1_target(void)
{
char *boot_targets = strdup(env_get("boot_targets"));
char *mmc1 = strstr(boot_targets, "mmc1");
if (mmc1) {
memmove(mmc1, mmc1 + 4, strlen(mmc1 + 4) + 1);
env_set("boot_targets", boot_targets);
}
free(boot_targets);
}
void set_board_info_env(void)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
u8 __maybe_unused mac_cnt;
const char *fdtfile;
if (info->magic != IOT2050_INFO_MAGIC) {
pr_err("IOT2050: Board info parsing error!\n");
return;
}
if (env_get("board_uuid"))
return;
env_set("board_name", info->name);
env_set("board_serial", info->serial);
env_set("mlfb", info->mlfb);
env_set("board_uuid", info->uuid);
env_set("board_a5e", info->a5e);
env_set("fw_version", PLAIN_VERSION);
env_set("seboot_version", info->seboot_version);
if (IS_ENABLED(CONFIG_NET)) {
/* set MAC addresses to ensure forwarding to the OS */
for (mac_cnt = 0; mac_cnt < info->mac_addr_cnt; mac_cnt++) {
if (is_valid_ethaddr(info->mac_addr[mac_cnt]))
eth_env_set_enetaddr_by_index("eth",
mac_cnt + 1,
info->mac_addr[mac_cnt]);
}
}
if (board_is_advanced()) {
if (board_is_sr1())
fdtfile = "ti/k3-am6548-iot2050-advanced.dtb";
else
fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb";
} else {
if (board_is_sr1())
fdtfile = "ti/k3-am6528-iot2050-basic.dtb";
else
fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb";
/* remove the unavailable eMMC (mmc1) from the list */
remove_mmc1_target();
}
env_set("fdtfile", fdtfile);
env_save();
}
int board_init(void)
{
return 0;
}
int dram_init(void)
{
if (board_is_advanced())
gd->ram_size = SZ_2G;
else
gd->ram_size = SZ_1G;
return 0;
}
int dram_init_banksize(void)
{
dram_init();
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
return 0;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
char upper_name[32];
if (info->magic != IOT2050_INFO_MAGIC ||
strlen(name) >= sizeof(upper_name))
return -1;
str_to_upper(name, upper_name, sizeof(upper_name));
if (!strcmp(upper_name, (char *)info->name))
return 0;
return -1;
}
#endif
int do_board_detect(void)
{
return 0;
}
#ifdef CONFIG_IOT2050_BOOT_SWITCH
static bool user_button_pressed(void)
{
struct udevice *red_led = NULL;
unsigned long count = 0;
struct gpio_desc gpio;
memset(&gpio, 0, sizeof(gpio));
if (dm_gpio_lookup_name("25", &gpio) < 0 ||
dm_gpio_request(&gpio, "USER button") < 0 ||
dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN) < 0)
return false;
if (dm_gpio_get_value(&gpio) == 1)
return false;
printf("USER button pressed - booting from external media only\n");
led_get_by_label("status-led-red", &red_led);
if (red_led)
led_set_state(red_led, LEDST_ON);
while (dm_gpio_get_value(&gpio) == 0 && count++ < 10000)
mdelay(1);
if (red_led)
led_set_state(red_led, LEDST_OFF);
return true;
}
#endif
#define SERDES0_LANE_SELECT 0x00104080
int board_late_init(void)
{
/* change CTRL_MMR register to let serdes0 not output USB3.0 signals. */
writel(0x3, SERDES0_LANE_SELECT);
set_board_info_env();
/* remove the eMMC if requested via button */
if (IS_ENABLED(CONFIG_IOT2050_BOOT_SWITCH) && board_is_advanced() &&
user_button_pressed())
remove_mmc1_target();
return 0;
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
int ret;
ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
if (ret < 0)
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
"sram@70000000");
if (ret)
pr_err("%s: fixing up msmc ram failed %d\n", __func__, ret);
return ret;
}
#endif
void spl_board_init(void)
{
}
#if CONFIG_IS_ENABLED(LED) && CONFIG_IS_ENABLED(BOOTSTAGE)
/*
* Indicate any error or (accidental?) entering of CLI via the red status LED.
*/
void show_boot_progress(int progress)
{
struct udevice *dev;
int ret;
if (progress < 0 || progress == BOOTSTAGE_ID_ENTER_CLI_LOOP) {
ret = led_get_by_label("status-led-green", &dev);
if (ret == 0)
led_set_state(dev, LEDST_OFF);
ret = led_get_by_label("status-led-red", &dev);
if (ret == 0)
led_set_state(dev, LEDST_ON);
}
}
#endif

8
board/siemens/iot2050/config.mk Normal file
View file

@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) Siemens AG, 2020-2021
#
# Authors:
# Jan Kiszka <jan.kiszka@siemens.com>
flash.bin: all

6
cmd/pci.c
View file

@ -59,7 +59,7 @@ static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
}
}
int pci_bar_show(struct udevice *dev)
static int pci_bar_show(struct udevice *dev)
{
u8 header_type;
int bar_cnt, bar_id, mem_type;
@ -223,7 +223,7 @@ static struct pci_reg_info regs_cardbus[] = {
*
* @dev: Bus+Device+Function number
*/
void pci_header_show(struct udevice *dev)
static void pci_header_show(struct udevice *dev)
{
unsigned long class, header_type;
@ -251,7 +251,7 @@ void pci_header_show(struct udevice *dev)
}
}
void pciinfo_header(int busnum, bool short_listing)
static void pciinfo_header(int busnum, bool short_listing)
{
printf("Scanning PCI devices on bus %d\n", busnum);

136
configs/iot2050_defconfig Normal file
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@ -0,0 +1,136 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_IOT2050_A53=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6a0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTSTAGE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SYS_PROMPT="IOT2050> "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="k3-am6528-iot2050-basic k3-am6548-iot2050-advanced"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_LED=y
CONFIG_SPL_LED=y
CONFIG_LED_GPIO=y
CONFIG_SPL_LED_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PCI=y
CONFIG_PCI_KEYSTONE=y
CONFIG_PHY=y
CONFIG_AM654_PHY=y
CONFIG_OMAP_USB2_PHY=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
# CONFIG_WATCHDOG is not set
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
CONFIG_WDT_K3_RTI=y
CONFIG_WDT_K3_RTI_LOAD_FW=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
doc/board/index.rst
View file

@ -22,6 +22,7 @@ Board-specific doc
openpiton/index
qualcomm/index
rockchip/index
siemens/index
sifive/index
sipeed/index
socionext/index

9
doc/board/siemens/index.rst Normal file
View file

@ -0,0 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0+
Siemens
=======
.. toctree::
:maxdepth: 2
iot2050

78
doc/board/siemens/iot2050.rst Normal file
View file

@ -0,0 +1,78 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Jan Kiszka <jan.kiszka@siemens.com>
SIMATIC IOT2050 BASIC and ADVANCED
==================================
The SIMATIC IOT2050 is an open industrial IoT gateway that is using the TI
AM6528 GP (Basic variant) or the AM6548 HS (Advanced variant). The Advanced
variant is prepared for secure boot.
The IOT2050 starts only from OSPI. It loads a Siemens-provided bootloader
called SE-Boot for the MCU domain (R5F cores), then hands over to ATF and
OP-TEE, before booting U-Boot on the A53 cores. This describes how to build all
open artifacts into a flashable image for the OSPI flash. The flash image will
work on both variants.
Dependencies
------------
ATF: Upstream release 2.4 or newer
OP-TEE: Upstream release 3.10.0 or newer
Binary dependencies can be found in
https://github.com/siemens/meta-iot2050/tree/master/recipes-bsp/u-boot/files/prebuild.
The following binaries from that source need to be present in the build folder:
- tiboot3.bin
- sysfw.itb
- sysfw.itb_HS
- sysfw_sr2.itb
- sysfw_sr2.itb_HS
Building
--------
Make sure that CROSS_COMPILE is set appropriately:
.. code-block:: text
$ export CROSS_COMPILE=aarch64-linux-gnu-
ATF:
.. code-block:: text
$ make PLAT=k3 SPD=opteed K3_USART=1
OP-TEE:
.. code-block:: text
$ make PLATFORM=k3-am65x CFG_ARM64_core=y CFG_TEE_CORE_LOG_LEVEL=2 CFG_CONSOLE_UART=1
U-Boot:
.. code-block:: text
$ export ATF=/path/to/bl31.bin
$ export TEE=/path/to/tee-pager_v2.bin
$ make iot2050_defconfig
$ make
Flashing
--------
Via U-Boot:
.. code-block:: text
IOT2050> sf probe
IOT2050> load mmc 0:1 $loadaddr /path/to/flash.bin
IOT2050> sf update $loadaddr 0x0 $filesize
Via external programmer Dediprog SF100 or SF600:
.. code-block:: text
$ dpcmd --vcc 2 -v -u flash.bin

14
drivers/pci/pci-uclass.c
View file

@ -304,8 +304,8 @@ int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
}
int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
enum pci_size_t size)
static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
enum pci_size_t size)
{
struct udevice *bus;
int ret;
@ -369,8 +369,8 @@ int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
return ops->read_config(bus, bdf, offset, valuep, size);
}
int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
enum pci_size_t size)
static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
enum pci_size_t size)
{
struct udevice *bus;
int ret;
@ -1426,9 +1426,9 @@ phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
return phys_addr;
}
int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
unsigned long flags, unsigned long skip_mask,
pci_addr_t *ba)
static int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
unsigned long flags, unsigned long skip_mask,
pci_addr_t *ba)
{
struct pci_region *res;
struct udevice *ctlr;

1
drivers/pci/pci_auto.c
View file

@ -12,6 +12,7 @@
#include <errno.h>
#include <log.h>
#include <pci.h>
#include "pci_internal.h"
/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE

3
drivers/pci/pcie_layerscape_fixup_common.c
View file

@ -12,6 +12,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include "pcie_layerscape_fixup_common.h"
void ft_pci_setup(void *blob, struct bd_info *bd)
@ -29,7 +30,7 @@ void ft_pci_setup(void *blob, struct bd_info *bd)
}
#if defined(CONFIG_FSL_LAYERSCAPE)
int lx2_board_fix_fdt(void *fdt)
static int lx2_board_fix_fdt(void *fdt)
{
char *reg_name, *old_str, *new_str;
const char *reg_names;

4
drivers/pci/pcie_layerscape_rc.c
View file

@ -143,8 +143,8 @@ static int ls_pcie_addr_valid(struct ls_pcie_rc *pcie_rc, pci_dev_t bdf)
return 0;
}
int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
uint offset, void **paddress)
static int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
uint offset, void **paddress)
{
struct ls_pcie_rc *pcie_rc = dev_get_priv(bus);
struct ls_pcie *pcie = pcie_rc->pcie;

1
drivers/rtc/Kconfig
View file

@ -136,6 +136,7 @@ config RTC_RX8010SJ
config RTC_RX8025
bool "Enable RX8025 driver"
depends on DM_RTC
help
Support for Epson RX8025 Real Time Clock devices.

164
drivers/rtc/rx8025.c
View file

@ -24,22 +24,11 @@
#endif
/*---------------------------------------------------------------------*/
#ifndef CONFIG_SYS_I2C_RTC_ADDR
# define CONFIG_SYS_I2C_RTC_ADDR 0x32
#endif
#ifdef CONFIG_DM_RTC
#define DEV_TYPE struct udevice
#else
/* Local udevice */
struct ludevice {
u8 chip;
enum rx_model {
model_rx_8025,
model_rx_8035,
};
#define DEV_TYPE struct ludevice
#endif
/*
* RTC register addresses
*/
@ -50,6 +39,7 @@ struct ludevice {
#define RTC_DATE_REG_ADDR 0x04
#define RTC_MON_REG_ADDR 0x05
#define RTC_YR_REG_ADDR 0x06
#define RTC_OFFSET_REG_ADDR 0x07
#define RTC_CTL1_REG_ADDR 0x0e
#define RTC_CTL2_REG_ADDR 0x0f
@ -74,39 +64,36 @@ struct ludevice {
* address in a first cycle that is terminated by
* a STOP condition. The chips needs a 'restart'
* sequence (start sequence without a prior stop).
* This driver has been written for a 4xx board.
* U-Boot's 4xx i2c driver is currently not capable
* to generate such cycles to some work arounds
* are used.
*/
/* static uchar rtc_read (uchar reg); */
#ifdef CONFIG_DM_RTC
/*
* on mpc85xx based board with DM and offset len 1
* accessing rtc works fine. May we can drop this ?
*/
#define rtc_read(reg) buf[(reg) & 0xf]
#else
#define rtc_read(reg) buf[((reg) + 1) & 0xf]
#endif
static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val);
static int rtc_write(struct udevice *dev, uchar reg, uchar val);
static int rx8025_is_osc_stopped(enum rx_model model, int ctrl2)
{
int xstp = ctrl2 & RTC_CTL2_BIT_XST;
/* XSTP bit has different polarity on RX-8025 vs RX-8035.
* RX-8025: 0 == oscillator stopped
* RX-8035: 1 == oscillator stopped
*/
if (model == model_rx_8025)
xstp = !xstp;
return xstp;
}
/*
* Get the current time from the RTC
*/
static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
static int rx8025_rtc_get(struct udevice *dev, struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year, ctl2;
uchar buf[16];
#ifdef CONFIG_DM_RTC
if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
#else
if (i2c_read(dev->chip, 0, 0, buf, 16)) {
#endif
printf("Error reading from RTC\n");
return -EIO;
}
@ -134,8 +121,7 @@ static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
printf("RTC: voltage drop detected\n");
rel = -1;
}
if (!(ctl2 & RTC_CTL2_BIT_XST)) {
if (rx8025_is_osc_stopped(dev->driver_data, ctl2)) {
printf("RTC: oscillator stop detected\n");
rel = -1;
}
@ -165,8 +151,21 @@ static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
/*
* Set the RTC
*/
static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp)
static int rx8025_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
{
/* To work around the read/write cycle issue mentioned
* at the top of this file, write all the time registers
* in one I2C transaction
*/
u8 write_op[8];
/* 2412 flag must be set before doing a RTC write,
* otherwise the seconds and minute register
* will be cleared when the flag is set
*/
if (rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412))
return -EIO;
DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
@ -174,50 +173,38 @@ static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp)
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)))
return -EIO;
write_op[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec);
write_op[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min);
write_op[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour);
write_op[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday);
write_op[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday);
write_op[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon);
write_op[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100);
write_op[RTC_OFFSET_REG_ADDR] = 0;
if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon)))
return -EIO;
if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday)))
return -EIO;
if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)))
return -EIO;
if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)))
return -EIO;
if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)))
return -EIO;
if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)))
return -EIO;
return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
return dm_i2c_write(dev, 0, &write_op[0], 8);
}
/*
* Reset the RTC
*/
static int rx8025_rtc_reset(DEV_TYPE *dev)
static int rx8025_rtc_reset(struct udevice *dev)
{
uchar buf[16];
uchar ctl2;
#ifdef CONFIG_DM_RTC
if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
#else
if (i2c_read(dev->chip, 0, 0, buf, 16)) {
#endif
printf("Error reading from RTC\n");
return -EIO;
}
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
if (dev->driver_data == model_rx_8035)
ctl2 &= ~(RTC_CTL2_BIT_XST);
else
ctl2 |= RTC_CTL2_BIT_XST;
return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2);
}
@ -225,17 +212,16 @@ static int rx8025_rtc_reset(DEV_TYPE *dev)
/*
* Helper functions
*/
static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val)
static int rtc_write(struct udevice *dev, uchar reg, uchar val)
{
uchar buf[2];
buf[0] = reg << 4;
buf[1] = val;
/* The RX8025/RX8035 uses the top 4 bits of the
* 'offset' byte as the start register address,
* and the bottom 4 bits as a 'transfer' mode setting
* (only applicable for reads)
*/
u8 offset = (reg << 4);
#ifdef CONFIG_DM_RTC
if (dm_i2c_write(dev, 0, buf, 2)) {
#else
if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) {
#endif
if (dm_i2c_reg_write(dev, offset, val)) {
printf("Error writing to RTC\n");
return -EIO;
}
@ -243,7 +229,6 @@ static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val)
return 0;
}
#ifdef CONFIG_DM_RTC
static int rx8025_probe(struct udevice *dev)
{
uchar buf[16];
@ -265,42 +250,15 @@ static const struct rtc_ops rx8025_rtc_ops = {
};
static const struct udevice_id rx8025_rtc_ids[] = {
{ .compatible = "epson,rx8025" },
{ .compatible = "epson,rx8025", .data = model_rx_8025 },
{ .compatible = "epson,rx8035", .data = model_rx_8035 },
{ }
};
U_BOOT_DRIVER(rx8010sj_rtc) = {
U_BOOT_DRIVER(rx8025_rtc) = {
.name = "rx8025_rtc",
.id = UCLASS_RTC,
.probe = rx8025_probe,
.of_match = rx8025_rtc_ids,
.ops = &rx8025_rtc_ops,
};
#else
int rtc_get(struct rtc_time *tm)
{
struct ludevice dev = {
.chip = CONFIG_SYS_I2C_RTC_ADDR,
};
return rx8025_rtc_get(&dev, tm);
}
int rtc_set(struct rtc_time *tm)
{
struct ludevice dev = {
.chip = CONFIG_SYS_I2C_RTC_ADDR,
};
return rx8025_rtc_set(&dev, tm);
}
void rtc_reset(void)
{
struct ludevice dev = {
.chip = CONFIG_SYS_I2C_RTC_ADDR,
};
rx8025_rtc_reset(&dev);
}
#endif

20
drivers/watchdog/Kconfig
View file

@ -218,6 +218,26 @@ config WDT_K3_RTI
Say Y here if you want to include support for the K3 watchdog
timer (RTI module) available in the K3 generation of processors.
if WDT_K3_RTI
config WDT_K3_RTI_LOAD_FW
bool "Load watchdog firmware"
depends on REMOTEPROC
help
Automatically load the specified firmware image into the MCU R5F
core 0. On the AM65x, this firmware is supposed to handle the expiry
of the watchdog timer, typically by resetting the system.
config WDT_K3_RTI_FW_FILE
string "Watchdog firmware image file"
default "k3-rti-wdt.fw"
depends on WDT_K3_RTI_LOAD_FW
help
Firmware image to be embedded into U-Boot and loaded on watchdog
start.
endif
config WDT_SANDBOX
bool "Enable Watchdog Timer support for Sandbox"
depends on SANDBOX && WDT

88
drivers/watchdog/rti_wdt.c
View file

@ -11,9 +11,11 @@
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <power-domain.h>
#include <wdt.h>
#include <asm/io.h>
#include <remoteproc.h>
/* Timer register set definition */
#define RTIDWDCTRL 0x90
@ -42,6 +44,88 @@ struct rti_wdt_priv {
unsigned int clk_khz;
};
#ifdef CONFIG_WDT_K3_RTI_LOAD_FW
#define RTI_WDT_FIT_PATH "/fit-images/k3-rti-wdt-firmware"
static int rti_wdt_load_fw(struct udevice *dev)
{
struct udevice *rproc_dev;
int primary_core, ret;
u32 cluster_mode;
ofnode node;
u64 rti_wdt_fw;
u32 rti_wdt_fw_size;
node = ofnode_path(RTI_WDT_FIT_PATH);
if (!ofnode_valid(node))
goto fit_error;
ret = ofnode_read_u64(node, "load", &rti_wdt_fw);
if (ret)
goto fit_error;
ret = ofnode_read_u32(node, "size", &rti_wdt_fw_size);
if (ret)
goto fit_error;
node = ofnode_by_compatible(ofnode_null(), "ti,am654-r5fss");
if (!ofnode_valid(node))
goto dt_error;
ret = ofnode_read_u32(node, "ti,cluster-mode", &cluster_mode);
if (ret)
cluster_mode = 1;
node = ofnode_by_compatible(node, "ti,am654-r5f");
if (!ofnode_valid(node))
goto dt_error;
ret = uclass_get_device_by_ofnode(UCLASS_REMOTEPROC, node, &rproc_dev);
if (ret)
return ret;
primary_core = dev_seq(rproc_dev);
ret = rproc_dev_init(primary_core);
if (ret)
goto fw_error;
if (cluster_mode == 1) {
ret = rproc_dev_init(primary_core + 1);
if (ret)
goto fw_error;
}
ret = rproc_load(primary_core, (ulong)rti_wdt_fw,
rti_wdt_fw_size);
if (ret)
goto fw_error;
ret = rproc_start(primary_core);
if (ret)
goto fw_error;
return 0;
fit_error:
dev_err(dev, "No loadable firmware found under %s\n", RTI_WDT_FIT_PATH);
return -ENOENT;
dt_error:
dev_err(dev, "No compatible firmware target processor found\n");
return -ENODEV;
fw_error:
dev_err(dev, "Failed to load watchdog firmware into remote processor %d\n",
primary_core);
return ret;
}
#else
static inline int rti_wdt_load_fw(struct udevice *dev)
{
return 0;
}
#endif
static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
struct rti_wdt_priv *priv = dev_get_priv(dev);
@ -51,6 +135,10 @@ static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY)
return -EBUSY;
ret = rti_wdt_load_fw(dev);
if (ret < 0)
return ret;
timer_margin = timeout_ms * priv->clk_khz / 1000;
timer_margin >>= WDT_PRELOAD_SHIFT;
if (timer_margin > WDT_PRELOAD_MAX)

62
include/configs/iot2050.h Normal file
View file

@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration header file for IOT2050
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*/
#ifndef __CONFIG_IOT2050_H
#define __CONFIG_IOT2050_H
#include <linux/sizes.h>
/* SPL Loader Configuration */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* U-Boot general configuration */
#define EXTRA_ENV_IOT2050_BOARD_SETTINGS \
"usb_pgood_delay=900\0"
#ifndef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(CMD_USB)
# define BOOT_TARGET_USB(func) \
func(USB, usb, 0) \
func(USB, usb, 1) \
func(USB, usb, 2)
#else
# define BOOT_TARGET_USB(func)
#endif
/*
* This defines all MMC devices, even if the basic variant has no mmc1.
* The non-supported device will be removed from the boot targets during
* runtime, when that board was detected.
*/
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
BOOT_TARGET_USB(func)
#include <config_distro_bootcmd.h>
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
BOOTENV \
EXTRA_ENV_IOT2050_BOARD_SETTINGS
#include <configs/ti_armv7_common.h>
#endif /* __CONFIG_IOT2050_H */

39
include/dt-bindings/net/ti-dp83867.h
View file

@ -1,7 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI DP83867 PHY drivers
* Device Tree constants for the Texas Instruments DP83867 PHY
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* Copyright: (C) 2015 Texas Instruments, Inc.
*/
#ifndef _DT_BINDINGS_TI_DP83867_H
@ -14,22 +17,22 @@
#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
/* RGMIIDCTL internal delay for rx and tx */
#define DP83867_RGMIIDCTL_250_PS 0x0
#define DP83867_RGMIIDCTL_500_PS 0x1
#define DP83867_RGMIIDCTL_750_PS 0x2
#define DP83867_RGMIIDCTL_1_NS 0x3
#define DP83867_RGMIIDCTL_1_25_NS 0x4
#define DP83867_RGMIIDCTL_1_50_NS 0x5
#define DP83867_RGMIIDCTL_1_75_NS 0x6
#define DP83867_RGMIIDCTL_2_00_NS 0x7
#define DP83867_RGMIIDCTL_2_25_NS 0x8
#define DP83867_RGMIIDCTL_2_50_NS 0x9
#define DP83867_RGMIIDCTL_2_75_NS 0xa
#define DP83867_RGMIIDCTL_3_00_NS 0xb
#define DP83867_RGMIIDCTL_3_25_NS 0xc
#define DP83867_RGMIIDCTL_3_50_NS 0xd
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
#define DP83867_RGMIIDCTL_250_PS 0x0
#define DP83867_RGMIIDCTL_500_PS 0x1
#define DP83867_RGMIIDCTL_750_PS 0x2
#define DP83867_RGMIIDCTL_1_NS 0x3
#define DP83867_RGMIIDCTL_1_25_NS 0x4
#define DP83867_RGMIIDCTL_1_50_NS 0x5
#define DP83867_RGMIIDCTL_1_75_NS 0x6
#define DP83867_RGMIIDCTL_2_00_NS 0x7
#define DP83867_RGMIIDCTL_2_25_NS 0x8
#define DP83867_RGMIIDCTL_2_50_NS 0x9
#define DP83867_RGMIIDCTL_2_75_NS 0xa
#define DP83867_RGMIIDCTL_3_00_NS 0xb
#define DP83867_RGMIIDCTL_3_25_NS 0xc
#define DP83867_RGMIIDCTL_3_50_NS 0xd
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
/* IO_MUX_CFG - Clock output selection */
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0

47
include/dt-bindings/pinctrl/k3.h
View file

@ -1,36 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for TI K3-AM65 pinctrl bindings.
* This header provides constants for pinctrl bindings for TI's K3 SoC
* family.
*
* Copyright (C) 2018-2021 Texas Instruments
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H
#define _DT_BINDINGS_PINCTRL_TI_K3_H
#define PULL_DISABLE (1 << 16)
#define PULL_UP (1 << 17)
#define INPUT_EN (1 << 18)
#define SLEWCTRL_200MHZ 0
#define SLEWCTRL_150MHZ (1 << 19)
#define SLEWCTRL_100MHZ (2 << 19)
#define SLEWCTRL_50MHZ (3 << 19)
#define TX_DIS (1 << 21)
#define ISO_OVR (1 << 22)
#define ISO_BYPASS (1 << 23)
#define DS_EN (1 << 24)
#define DS_INPUT (1 << 25)
#define DS_FORCE_OUT_HIGH (1 << 26)
#define DS_PULL_UP_DOWN_EN 0
#define DS_PULL_UP_DOWN_DIS (1 << 27)
#define DS_PULL_UP_SEL (1 << 28)
#define WAKEUP_ENABLE (1 << 29)
#define PULLUDEN_SHIFT (16)
#define PULLTYPESEL_SHIFT (17)
#define RXACTIVE_SHIFT (18)
#define PIN_OUTPUT (PULL_DISABLE)
#define PIN_OUTPUT_PULLUP (PULL_UP)
#define PIN_OUTPUT_PULLDOWN 0
#define PULL_DISABLE (1 << PULLUDEN_SHIFT)
#define PULL_ENABLE (0 << PULLUDEN_SHIFT)
#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE)
#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE)
#define INPUT_EN (1 << RXACTIVE_SHIFT)
#define INPUT_DISABLE (0 << RXACTIVE_SHIFT)
/* Only these macros are expected be used directly in device tree files */
#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE)
#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP)
#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN)
#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (INPUT_EN)
#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN)
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))

2
include/pci.h
View file

@ -724,6 +724,7 @@ void pciauto_config_init(struct pci_controller *hose);
*/
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
pci_addr_t *bar, bool supports_64bit);
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
#if defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
@ -741,7 +742,6 @@ extern struct pci_controller* pci_bus_to_hose(int bus);
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
extern struct pci_controller *pci_get_hose_head(void);
extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);

5
tools/binman/missing-blob-help
View file

@ -17,3 +17,8 @@ board/sunxi/README.sunxi64
scp-sunxi:
SCP firmware is required for system suspend, but is otherwise optional.
Please read the section on SCP firmware in board/sunxi/README.sunxi64
k3-rti-wdt-firmware:
If CONFIG_WDT_K3_RTI_LOAD_FW is enabled, a firmware image is needed for
the R5F core(s) to trigger the system reset. One possible source is
https://github.com/siemens/k3-rti-wdt.