mirror of
https://github.com/Fishwaldo/u-boot.git
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Merge git://git.denx.de/u-boot-mips
This commit is contained in:
commit
fcc8250c2f
14 changed files with 59 additions and 24 deletions
1
.mailmap
1
.mailmap
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@ -20,6 +20,7 @@ Jagan Teki <jaganna@xilinx.com>
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Jagan Teki <jagannadh.teki@gmail.com>
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Jagan Teki <jagannadh.teki@gmail.com>
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Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
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Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
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Markus Klotzbuecher <mk@denx.de>
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Markus Klotzbuecher <mk@denx.de>
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Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
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Prabhakar Kushwaha <prabhakar@freescale.com>
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Prabhakar Kushwaha <prabhakar@freescale.com>
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Rajeshwari Shinde <rajeshwari.s@samsung.com>
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Rajeshwari Shinde <rajeshwari.s@samsung.com>
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Ricardo Ribalda <ricardo.ribalda@uam.es>
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Ricardo Ribalda <ricardo.ribalda@uam.es>
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@ -5,12 +5,6 @@
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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#if defined(CONFIG_64BIT)
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#define PTR_COUNT_SHIFT 3
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#else
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#define PTR_COUNT_SHIFT 2
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#endif
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OUTPUT_ARCH(mips)
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OUTPUT_ARCH(mips)
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ENTRY(_start)
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ENTRY(_start)
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SECTIONS
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SECTIONS
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@ -14,8 +14,10 @@
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#ifndef _ASM_SYSTEM_H
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <asm/asm.h>
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#include <asm/sgidefs.h>
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#include <asm/sgidefs.h>
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#include <asm/ptrace.h>
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#include <asm/ptrace.h>
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#include <linux/stringify.h>
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#if 0
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#if 0
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#endif
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#endif
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@ -270,4 +272,15 @@ static inline void execution_hazard_barrier(void)
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".set reorder");
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".set reorder");
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}
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}
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static inline void instruction_hazard_barrier(void)
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{
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unsigned long tmp;
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asm volatile(
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__stringify(PTR_LA) "\t%0, 1f\n"
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" jr.hb %0\n"
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"1: .insn"
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: "=&r"(tmp));
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}
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#endif /* _ASM_SYSTEM_H */
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#endif /* _ASM_SYSTEM_H */
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@ -10,7 +10,9 @@
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#ifdef CONFIG_MIPS_L2_CACHE
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#ifdef CONFIG_MIPS_L2_CACHE
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#include <asm/cm.h>
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#include <asm/cm.h>
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#endif
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#endif
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -96,6 +98,9 @@ static inline unsigned long scache_line_size(void)
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const unsigned int cache_ops[] = { ops }; \
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const unsigned int cache_ops[] = { ops }; \
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unsigned int i; \
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unsigned int i; \
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\
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\
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if (!lsize) \
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break; \
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\
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for (; addr <= aend; addr += lsize) { \
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for (; addr <= aend; addr += lsize) { \
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for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
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for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
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mips_cache(cache_ops[i], addr); \
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mips_cache(cache_ops[i], addr); \
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@ -116,19 +121,24 @@ void flush_cache(ulong start_addr, ulong size)
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/* flush I-cache & D-cache simultaneously */
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/* flush I-cache & D-cache simultaneously */
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cache_loop(start_addr, start_addr + size, ilsize,
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cache_loop(start_addr, start_addr + size, ilsize,
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HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
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HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
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return;
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goto ops_done;
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}
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}
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/* flush D-cache */
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/* flush D-cache */
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cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
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cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
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/* flush L2 cache */
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/* flush L2 cache */
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if (slsize)
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cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
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cache_loop(start_addr, start_addr + size, slsize,
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HIT_WRITEBACK_INV_SD);
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/* flush I-cache */
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/* flush I-cache */
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cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
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cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
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ops_done:
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/* ensure cache ops complete before any further memory accesses */
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sync();
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/* ensure the pipeline doesn't contain now-invalid instructions */
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instruction_hazard_barrier();
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}
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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void flush_dcache_range(ulong start_addr, ulong stop)
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@ -143,8 +153,10 @@ void flush_dcache_range(ulong start_addr, ulong stop)
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cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
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cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
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/* flush L2 cache */
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/* flush L2 cache */
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if (slsize)
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cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
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cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
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/* ensure cache ops complete before any further memory accesses */
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sync();
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}
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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@ -157,8 +169,10 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
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return;
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return;
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/* invalidate L2 cache */
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/* invalidate L2 cache */
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if (slsize)
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cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
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cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
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cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
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cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
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/* ensure cache ops complete before any further memory accesses */
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sync();
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}
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}
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@ -1,5 +1,5 @@
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BOSTON BOARD
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BOSTON BOARD
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M: Paul Burton <paul.burton@imgtec.com>
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M: Paul Burton <paul.burton@mips.com>
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S: Maintained
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S: Maintained
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F: board/imgtec/boston/
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F: board/imgtec/boston/
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F: include/configs/boston.h
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F: include/configs/boston.h
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14
board/imgtec/boston/config.mk
Normal file
14
board/imgtec/boston/config.mk
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@ -0,0 +1,14 @@
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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quiet_cmd_srec_cat = SRECCAT $@
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cmd_srec_cat = srec_cat -output $@ -$2 $< -binary -offset $3
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u-boot.mcs: u-boot.bin
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$(call cmd,srec_cat,intel,0x7c00000)
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# if srec_cat is present build u-boot.mcs by default
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has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
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ALL-$(has_srec_cat) += u-boot.mcs
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CLEAN_FILES += u-boot.mcs
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@ -34,7 +34,6 @@ LEAF(lowlevel_init)
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PTR_LA a0, msg_ddr_ok
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PTR_LA a0, msg_ddr_ok
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bal lowlevel_display
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bal lowlevel_display
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move v0, zero
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jr s0
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jr s0
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END(lowlevel_init)
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END(lowlevel_init)
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@ -52,5 +51,5 @@ LEAF(lowlevel_display)
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sw k1, 4(AT)
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sw k1, 4(AT)
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#endif
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#endif
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.set pop
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.set pop
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1: jr ra
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jr ra
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END(lowlevel_display)
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END(lowlevel_display)
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@ -1,5 +1,5 @@
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MALTA BOARD
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MALTA BOARD
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M: Paul Burton <paul.burton@imgtec.com>
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M: Paul Burton <paul.burton@mips.com>
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S: Maintained
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S: Maintained
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F: board/imgtec/malta/
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F: board/imgtec/malta/
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F: include/configs/malta.h
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F: include/configs/malta.h
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@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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* Author: Paul Burton <paul.burton@mips.com>
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*
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*
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* Setup code for the FDC37M817 super I/O controller
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* Setup code for the FDC37M817 super I/O controller
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*
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*
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@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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* Author: Paul Burton <paul.burton@mips.com>
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*
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*
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* Setup code for the FDC37M817 super I/O controller
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* Setup code for the FDC37M817 super I/O controller
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*
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*
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@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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* Author: Paul Burton <paul.burton@mips.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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@ -34,7 +34,7 @@
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
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@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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* Author: Paul Burton <paul.burton@mips.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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* Author: Paul Burton <paul.burton@mips.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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