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spi: davinci_spi: Driver cleanup
Arrange driver code in more readable format[1] for easy accessing and readable. [1] http://patchwork.ozlabs.org/patch/265683/ Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Rex Chang <rchang@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
This commit is contained in:
Jagan Teki
parent
e6d2fbf70a
commit
ff6e31d3a1
1 changed files with 173 additions and 170 deletions
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@ -8,39 +8,13 @@
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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struct davinci_spi_regs {
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dv_reg gcr0; /* 0x00 */
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dv_reg gcr1; /* 0x04 */
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dv_reg int0; /* 0x08 */
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dv_reg lvl; /* 0x0c */
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dv_reg flg; /* 0x10 */
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dv_reg pc0; /* 0x14 */
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dv_reg pc1; /* 0x18 */
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dv_reg pc2; /* 0x1c */
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dv_reg pc3; /* 0x20 */
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dv_reg pc4; /* 0x24 */
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dv_reg pc5; /* 0x28 */
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dv_reg rsvd[3];
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dv_reg dat0; /* 0x38 */
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dv_reg dat1; /* 0x3c */
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dv_reg buf; /* 0x40 */
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dv_reg emu; /* 0x44 */
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dv_reg delay; /* 0x48 */
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dv_reg def; /* 0x4c */
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dv_reg fmt0; /* 0x50 */
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dv_reg fmt1; /* 0x54 */
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dv_reg fmt2; /* 0x58 */
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dv_reg fmt3; /* 0x5c */
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dv_reg intvec0; /* 0x60 */
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dv_reg intvec1; /* 0x64 */
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};
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#define BIT(x) (1 << (x))
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/* SPIGCR0 */
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@ -112,6 +86,35 @@ struct davinci_spi_regs {
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#define SPI2_BASE CONFIG_SYS_SPI2_BASE
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#endif
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/* davinci spi register set */
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struct davinci_spi_regs {
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dv_reg gcr0; /* 0x00 */
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dv_reg gcr1; /* 0x04 */
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dv_reg int0; /* 0x08 */
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dv_reg lvl; /* 0x0c */
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dv_reg flg; /* 0x10 */
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dv_reg pc0; /* 0x14 */
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dv_reg pc1; /* 0x18 */
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dv_reg pc2; /* 0x1c */
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dv_reg pc3; /* 0x20 */
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dv_reg pc4; /* 0x24 */
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dv_reg pc5; /* 0x28 */
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dv_reg rsvd[3];
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dv_reg dat0; /* 0x38 */
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dv_reg dat1; /* 0x3c */
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dv_reg buf; /* 0x40 */
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dv_reg emu; /* 0x44 */
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dv_reg delay; /* 0x48 */
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dv_reg def; /* 0x4c */
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dv_reg fmt0; /* 0x50 */
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dv_reg fmt1; /* 0x54 */
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dv_reg fmt2; /* 0x58 */
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dv_reg fmt3; /* 0x5c */
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dv_reg intvec0; /* 0x60 */
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dv_reg intvec1; /* 0x64 */
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};
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/* davinci spi slave */
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struct davinci_spi_slave {
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struct spi_slave slave;
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struct davinci_spi_regs *regs;
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@ -123,111 +126,6 @@ static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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void spi_init()
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct davinci_spi_slave *ds;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
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if (!ds)
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return NULL;
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switch (bus) {
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case SPI0_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
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break;
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#endif
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default: /* Invalid bus number */
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return NULL;
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}
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ds->freq = max_hz;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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free(ds);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int scalar;
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/* Enable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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udelay(1000);
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writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
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/* Set master mode, powered up and not activated */
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
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/*
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* Use following format:
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* character length = 8,
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* clock signal delayed by half clk cycle,
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* clock low in idle state - Mode 0,
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* MSB shifted out first
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*/
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writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
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(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
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/*
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* Including a minor delay. No science here. Should be good even with
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* no delay
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*/
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writel((50 << SPI_C2TDELAY_SHIFT) |
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(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
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/* default chip select register */
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writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
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/* no interrupts */
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writel(0, &ds->regs->int0);
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writel(0, &ds->regs->lvl);
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/* enable SPI */
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writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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/* Disable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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}
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/*
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* This functions needs to act like a macro to avoid pipeline reloads in the
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* loops below. Use always_inline. This gains us about 160KiB/s and the bloat
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@ -343,6 +241,149 @@ static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
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}
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#endif
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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int ret = 0;
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switch (bus) {
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case SPI0_BUS:
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if (cs < SPI0_NUM_CS)
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ret = 1;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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if (cs < SPI1_NUM_CS)
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ret = 1;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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if (cs < SPI2_NUM_CS)
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ret = 1;
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break;
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#endif
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default:
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/* Invalid bus number. Do nothing */
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break;
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}
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return ret;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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void spi_init(void)
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct davinci_spi_slave *ds;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
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if (!ds)
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return NULL;
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switch (bus) {
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case SPI0_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
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break;
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#endif
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default: /* Invalid bus number */
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return NULL;
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}
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ds->freq = max_hz;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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free(ds);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int scalar;
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/* Enable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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udelay(1000);
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writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
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/* Set master mode, powered up and not activated */
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
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/*
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* Use following format:
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* character length = 8,
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* clock signal delayed by half clk cycle,
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* clock low in idle state - Mode 0,
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* MSB shifted out first
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*/
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writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
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(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
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/*
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* Including a minor delay. No science here. Should be good even with
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* no delay
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*/
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writel((50 << SPI_C2TDELAY_SHIFT) |
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(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
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/* default chip select register */
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writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
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/* no interrupts */
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writel(0, &ds->regs->int0);
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writel(0, &ds->regs->lvl);
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/* enable SPI */
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writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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/* Disable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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@ -386,41 +427,3 @@ out:
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}
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return 0;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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int ret = 0;
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switch (bus) {
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case SPI0_BUS:
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if (cs < SPI0_NUM_CS)
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ret = 1;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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if (cs < SPI1_NUM_CS)
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ret = 1;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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if (cs < SPI2_NUM_CS)
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ret = 1;
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break;
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#endif
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default:
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/* Invalid bus number. Do nothing */
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break;
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}
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return ret;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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