Add different domain in dts node for sbi boot and disable
gmac1 node.
make DEVICE_TREE=starfive_jh7110-amp to build
uboot amp image.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
As drivers/video/raydium-rm68200-starfive.c is renamed to
drivers/video/starfive_seeed_panel.c, change the dts accordingly.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add device tree for StarFive JH7110 Devkits board.
The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
To be compatible with the Devkits board.
The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add board support for StarFive Devkits.
The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add device tree for StarFive VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
To be compatible with the VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add board support for StarFive VisionFive 2.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add a header to easily use the EEPROM interface.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Updated USB Device Tree Node to support USB Device functionality and is
consistent with Kernel.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
The frequency of cclk_in is limited to 50M, so that it does not do internal
part frequency and goes by-pass mode. And delete syscon node.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Starting from gcc 12.x, csr and fence instructions have been
separated from the base I instruction set. special the
zicsr_zifencei string to DT riscv,isa string
Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
class 8 and class9 cpu stall cycles hwcounter is
not supported in U74. delete the configuration.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a
compiled for double-float. To link to it we have to adjust how we build
U-Boot.
As U-Boot actually does not use floating point at all this should not
make a significant difference for the produced binaries.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Christian Stewart <christian@paral.in>
Reviewed-by: Rick Chen <rick@andestech.com>
This patch explicitly excludes the memory range of the OpenSBI in the
built-in device tree. When booting EFI, the efi loader has to know
about that zone before loading the device tree for Linux, otherwise
it tries to access 0x40000000, leading to an access violation.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
