u-boot/drivers/ddr
Chris Packham 40ed88529c mv_ddr: ddr3: Use correct bitmask for read sample delay
In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
extracting the value.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-09 06:49:44 +02:00
..
altera common: Drop linux/bitops.h from common header 2020-05-18 21:19:23 -04:00
fsl ddr: Rework errata A008109, A008378, 009942 workaround 2020-06-04 18:53:20 +05:30
imx common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
marvell mv_ddr: ddr3: Use correct bitmask for read sample delay 2020-07-09 06:49:44 +02:00
microchip SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
Kconfig drivers: ddr: introduce DDR driver for i.MX8M 2019-01-01 14:12:18 +01:00