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Author SHA1 Message Date
yanhong.wang
283a338dce riscv:dts:starfive-jh7110: modify Model and riscv,isa info 
Change Model to "StarFive JH7110 EVB", and change riscv,isa to
"rv64imafdcbsux"

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:37 +08:00
yanhong.wang
b04743f040 ram:starfive: Make ddr driver support 2G size 
The ddr driver include two configs with 2G and 4G.Fist read the ddr size
config from the memory node in the dts,then match the right config and
do it.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:37 +08:00
yanhong.wang
b8c8323ddd reset:starfive:jh7110: Delete redundant logic 
In the hardware design, the IPs RESET signal of jh7110 is divided into
two groups,one group is active high, and the other group is active low.

However, the software does not need to distinguish whether the RESET
signal is active high or active low,Write 1 to be assert, and write 0 to deassert.

Therefore, the software does not need to add additional logic to
distinguish these two sets of signals.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:37 +08:00
samin
d21940b4fc clk:jh7110: pll0 dynamically gets the frequency 
pll0 dynamically gets the frequency.

Signed-off-by: samin <samin.guo@starfivetech.com>
 2022-10-18 16:24:37 +08:00
samin
66107c3e05 spl:starfive: Add support for different CPU frequencies. 
The cpu uses 1.25G by default.

Lists of frequencies(MHz):

-375/500/625/750/875/1000/1250
-1375/1500/1625/1750/1800

Note: Some frequencies require voltage regulation.

Signed-off-by: samin <samin.guo@starfivetech.com>
 2022-10-18 16:24:37 +08:00
samin
90a8248c00 spl:starfive: remove function spl_cpu_fre_150/125 
replace them with spl_cpu_set_rate.

Signed-off-by: samin <samin.guo@starfivetech.com>
 2022-10-18 16:24:37 +08:00
yanhong.wang
61f294b11c board:starfive:evb: update uart3-uart5 resets 
Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive
JH7110 SoC.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:37 +08:00
yanhong.wang
abd35ca6d3 SPL:reset:starfive-jh7110: support reset in SPL 
Update Kconfig to support reset in SPL for StarFive JH7110 SoC.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:37 +08:00
yanhong.wang
4806c43e7a clk:riscv:starfive: update uart3-uart5 clks 
Update uart3-uart5 clks register info for StarFive JH7110 SoC.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
98ef3602a1 serial: ns16550: support a list of clk 
Add a list of clk enable operation.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
16178e355d SPL:starfive-jh7110: Modify the default division factor of sdcard clk 
Modify the default division factor of sdcard clk to 4.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
5531f12c6e board:starfive:evb: add usb init config 
Add usb init config for starfive EVB board. Default set to  USB2.0

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
0b2572d997 clk:starfive-jh7110: Update pll0/pll1/pll2 clk 
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to  clk-jh7110.c

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
b239f16521 net:phy:YUTAI: change tx delay config 
Modify the tx delay configuration.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
samin
1f6321dbaf spl: satrfive: bus_root switch to pll2. 
High-speed emmc/sdio support

Signed-off-by: samin <samin.guo@starfivetech.com>
 2022-10-18 16:24:36 +08:00
samin
fc05902d00 spl:gpio: Set GPIO domain0-3 voltage to 1.8V 
The default GPIO domian0-3 voltage is 3.3V, which is controlled by 4
bits. 0 means 3.3.V, 1 means 1.8V.

Signed-off-by: samin <samin.guo@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
9ca1a627b4 board:starfive:evb: modify the GPIO configuration for sd module 
Modify the GPIO configuration for sd&emmc module, switch the clk of  sd&emmc
to high frequency

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
967e3296ed riscv:dts:starfive-jh7110: Modify sd node configuration 
Modify SD&EMMC node configuration on Starfive EVB board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
c43d281323 SPL:riscv:starfive-jh7110: Adjust CPU working frequency 
Adjust CPU working frequency from 1G to 1.25G for starfive EVB board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
8a8168dd0c config:starfive-jh7110: add MICREL phy config to defconfig 
Add MICREL phy config to defconfig for starfive EVB board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
fb8cb55de3 board:starfive: enable prefetcher and add two macaddress configuration 
Add two macaddress for gmac0 and gmac1. Enable prefetcher for EVB board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
6bf1de16aa riscv:dts:starfive-jh7110: add ethernet-phy delay_chain config 
Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB
board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
3b92ff6927 clk:starfive-jh7110: add JH7110_GMAC1_GTXC clk 
Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:36 +08:00
yanhong.wang
87549bf093 net:dwc_eth_qos:starfive: remove phy-reset-gpio set 
Phy-reset-gpio set is unused in JH7110

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
41f9b1fe8d board:starfive: Modify dynamic alloc memory start addr in SPL 
Modify the dynamic alloc memory start address from L2 LIM to DDR.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
00018eb98a riscv:starfive-jh7110: clear L2 LIM memory 
Clear L2 LIM memory on StarFive  JH7110, avoid some unexpect exception.
 2022-10-18 16:24:35 +08:00
yanhong.wang
845221c93f config:starfive-jh7110: update starfive evb board default config 
Add DDR config to the default config for starfive evb board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
6f0b30d82c riscv:dts:starfive-jh7110: add ddr device node 
Add ddr device node for JH7110.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
0eddcac0de board:starfive: add clk init 
Add clk init for ddr on JH7110 board

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
b8ceeb8238 ram:starfive: add ddr driver 
Add driver for JH7110 to support ddr initialization in SPL.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Signed-off-by: samin <samin.guo@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
db61964dc2 net: dwc_eth_qos:starfive: update clk init 
Modify the clk init code for StarFive JH7110 platform.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
76c3fe3888 clk:starfive-jh7110: Update pll0/pll1/pll2 clk 
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define
from clk-jh7110.c  to jh7110_clk.dts

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
f785501c47 net:phy:YUTAI: Add delay chain 
Add tx/rx delay chain for YUTAI 8521

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
cafd9e471a GPIO:Starfive-jh7110: Add macro definition 
Add macro definition of GPIO

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
e81a6b4b7a board:starfive: add starfive evb board support 
Add board support for StarFive EVB.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
987a20bf9b clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macros 
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
2f5b272861 reset:starfive-jh7110: Adjust the dependency of RESET_JH7110 macro 
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to
STARFIVE_JH7110.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
becd46e208 riscv:dts: update clk&reset properties 
Synchronize the kernel dts file

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:35 +08:00
yanhong.wang
90afdef187 clk:starfive-jh7110: remove unused clk 
Remove unused clock in order to reduce code size.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
17a76df997 net:phy:YUTAI: Add YT8511/yt8521 phy init 
Add phy init for YUTAI YT8511/YT8521.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
66ede3957c net:phy:YUTAI: Add YT8511/yt8521 phy driver 
This adds basic support for YUTAI YT8511/YT8521  phy.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
11477926e3 usb:cdns3:Add StarFive wrapper driver for CDNS USB3 controller 
Add driver to handle StarFive  specific wrapper for Cadence USB3 controller
present on JH7110  SoC.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
a014f51a86 riscv:dts: update clk&reset properties 
Synchronize the kernel dts file

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
c7889a1007 reset:starfive: Adjust judgment conditions 
The  serial driver will call reset driver, udelay function will be called in reset driver,
but the timer is not init,so udelay function call will cases error.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
f95a5cec9f board:starfive: add rtc timer init 
The rtc timer is used early in kernel, but the clk&reset driver is not
ready,so some clk&reset init  is placed here.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
3d8b5aeca1 script: add execute permission 
Add executable permissions for script files. /*do not upstream*/

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
e143a581a3 config:starfive-jh7110: add config file for jh7110 
Add basic config option for StarFive VisionFive board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
dffb8ea8dd net:phy: add 10/100M register configuration 
Support 10/100M configuration.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
d3c8386d64 board:starfive: add starfive visionfive board support 
Add board support for StarFive VisionFive.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00
yanhong.wang
461cd1afbe net: dwc_eth_qos:starfive: add jh7110 support 
Add new configuration for jh7110 soc platform.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
 2022-10-18 16:24:34 +08:00