Heinrich Schuchardt
b680cc70dc
sysreset: provide SBI based sysreset driver
...
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-02-02 19:11:45 +08:00
Heinrich Schuchardt
c9051a2bda
riscv: add missing SBI extension definitions
...
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-02-02 19:11:40 +08:00
andy.hu
8571717e56
Merge branch 'CR_3068_DEFCONFIG_yanhong.wang' into 'jh7110-master'
...
CR 3068 configs: starfive-jh7110: update the value of CONFIG_SYS_MALLOC_F_LEN
See merge request sdk/u-boot!25
2023-01-11 11:11:51 +00:00
andy.hu
2e9bf27992
Merge branch 'CR_3067_add_boot_hard_id_minda' into 'jh7110-master'
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CR_3067 dts: add boot-hart-id property in dts
See merge request sdk/u-boot!24
2023-01-11 11:11:12 +00:00
Yanhong Wang
c84fa4dc98
configs: starfive-jh7110: update the value of CONFIG_SYS_MALLOC_F_LEN
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Update the value of CONFIG_SYS_MALLOC_F_LEN from 0x8000 to 0x10000.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-11 17:41:51 +08:00
minda.chen
ac7891c717
dts: add boot-hart-id property in dts
...
boot-hart-id is used by opensbi.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-09 15:19:09 +08:00
andy.hu
bfbdce9b86
Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-master'
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CR_3049 dts: add i2c5 and attach pmic configuration
See merge request sdk/u-boot!22
2023-01-06 06:41:29 +00:00
andy.hu
ea54199468
Merge branch 'CR_3006_OTP_yanhong.wang' into 'jh7110-master'
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CR_3006 misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read
See merge request sdk/u-boot!21
2023-01-06 06:25:28 +00:00
andy.hu
84e25a12dc
Merge branch 'CR_2708_VOUTCLK_yanhong.wang' into 'jh7110-master'
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CR 2708 clk:starfive: Add vout clock driver for StarFive JH7110
See merge request sdk/u-boot!23
2023-01-06 06:24:28 +00:00
andy.hu
f267373f7d
Merge branch 'CR_2828_perf_support_minda' into 'jh7110-master'
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CR_2828 dts: pmu : add riscv pmu dts config
See merge request sdk/u-boot!20
2023-01-06 06:14:49 +00:00
Yanhong Wang
1b96445bfc
clk:starfive: Add vout clock driver for StarFive JH7110
...
Add vout clock driver for StarFive JH7110
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-05 18:04:26 +08:00
minda.chen
946b2e1ad8
dts: add i2c5 and attach pmic configuration
...
i2c5 and pmic is used by opensbi power management
ops.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-05 13:15:42 +08:00
minda.chen
097a45c6a9
dts: pmu : add riscv pmu dts config
...
add 7110 performance monitor for perf use
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03 14:13:57 +08:00
Yanhong Wang
4db1f73604
misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read
...
Update the return value to match the function prototype definition.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-03 10:24:26 +08:00
andy.hu
8a4e190ee2
Merge branch 'CR_2876_SET_CPU_FREQ_samin.guo' into 'jh7110-master'
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CR_2876: board:starfive:evb: Set the CPU default frequency to 1.0GHz
See merge request sdk/u-boot!19
2022-12-19 04:04:34 +00:00
Samin Guo
699c0a8034
board:starfive:jh7110: Set the CPU default frequency to 1000MHz
...
Set to 1000M to ensure the CPU can work normally under 0.8V`
voltage
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-12-16 13:58:17 +08:00
Samin Guo
9b71c6f5fa
board:starfive:jh7110: default cpufreq is 1000Mhz.
...
The frequency of pll0 is set to 1000Mhz in the bootrom
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-12-14 18:12:52 +08:00
andy.hu
5d23c49f8e
Merge branch 'CR_2709_pinctrl_jianlong' into 'jh7110-master'
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CR_2709 dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
See merge request sdk/u-boot!18
2022-11-25 10:41:42 +00:00
Jianlong Huang
4cc82557a5
board:starfive:Remove usb/sdio0/sdio1 gpio init
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Remove usb/sdio0/sdio1 gpio init.
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-23 11:39:26 +08:00
Jianlong Huang
68dc790627
dts:starfive:Add pinctrl config
...
Add pinctrl config about usb/sdio0
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-23 11:38:24 +08:00
Jianlong Huang
ee772d8aea
configs: Enable STARFIVE_PINCTRL
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Enable STARFIVE_PINCTRL and PINCTRL_FULL
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21 11:55:32 +08:00
Kuan Lim Lee
b69d2e5f56
pinctrl: starfive: Add StarFive JH7110 driver
...
Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21 11:44:55 +08:00
Jianlong Huang
1288948b54
dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
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Add pinctrl definitions for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21 11:44:15 +08:00
andy.hu
2a2a3884ca
Merge branch 'CR_2555_CMA_samin.guo' into 'jh7110-master'
...
CR_2555: borad:jh7110:evb: Modify ramdisk_addr_r/pxefile_addr_r/scriptaddr
See merge request sdk/u-boot!17
2022-11-09 13:44:23 +00:00
Samin Guo
c6a5bf91e2
borad:jh7110:evb: Modify ramdisk_addr_r/pxefile_addr_r/scriptaddr
...
The jh7110 ddr starts from 0x40000000. Using 0x80000000 may cause the
CMA space to fail
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-09 17:04:00 +08:00
andy.hu
3853ecfd3c
Merge branch 'CR_2522_ECO_EVB_samin.guo' into 'jh7110-master'
...
CR_2522: support gamc with jh7110B-evb
See merge request sdk/u-boot!16
2022-11-02 10:02:27 +00:00
Samin Guo
bf2eae30d4
driver:qspi: Switch the QSPI parent clock to pll0
...
Switch the QSPI parent clock to pll0 to improve the QSPI speed
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-02 12:45:48 +08:00
Samin Guo
945a1c0027
spl:starfive:jh7110: Improved GMAC0/1 TX I/O PAD capability
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JH7110B requires a higher IOPAD capability in 1000M mode.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01 18:54:21 +08:00
Samin Guo
ca91f535d4
board:starfive:evb: Support using env to detect board version
...
JH7110B need tx_inverted by YT8521 phy, you need to read the chip
version to determine whether to use it.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01 18:54:21 +08:00
Samin Guo
0dbe3fb0be
board:starfive:evb: add get_chip_type
...
Read the chip model from the rgpio3 and setenv "chip_vision"
1: jh7110B
0: JH7110A
defalut: JH7110A
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01 18:54:30 +08:00
Samin Guo
bd7deb0588
board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmii
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JH7110B needs switch gmac0/1 tx to rgmii phy.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01 18:54:21 +08:00
Samin Guo
460fe5dd0b
dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.
...
JH7110B requires tx_inverted_10/100/1000 configuration, and different
parameters
may be required in 10M/100M/1000M mode.
This parameter supports JH7110B+YT8531PHY by default. Other boards can
modify the parameters of the tx_inverted_10/100/1000 to obtain support.
If you do not configure tx_inverted_10/100/1000 in dts, the default is
0.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01 16:24:08 +08:00
Samin Guo
fe0ba7e18e
net:phy:motorcomm: Support modifying RGMII_TX_CLK delay train from dts
...
support use original or inverted RGMII_TX_CLK delay train.
10M/100M/1000M can be configured independently.
tx_inverted_xx = val;
For example:
&gmac0 {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
tx_inverted_10 = <0>;
tx_inverted_100 = <1>;
tx_inverted_1000 = <1>;
};
};
0: original (default)
1: inverted
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01 09:38:54 +08:00
Yan Hong Wang
10ee04a535
ram: starfive: Make DDR driver support 8G size
...
This patch include four items:
1.rename the driver compatible name.
2.reset action with the common API.
3.clean up code to make it is closer to readable.
4.add configuration to support 8G size
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18 16:24:38 +08:00
Yan Hong Wang
7efb109f1d
riscv: dts: jh7110: Add reset property to DDR control node
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Add reset property configuration to DDR control device tree node.
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18 16:24:38 +08:00
Yan Hong Wang
6c18803bcb
ram: starfive: jh7110: Replace the configuration operation for pll1 clk
...
Replace the configuration operation for pll1 clk with common api provide
by pll module.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:38 +08:00
Yan Hong Wang
0c1fefaf48
clk: starfive: jh7110: Modify the parameters of clk_register()
...
Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:38 +08:00
Yan Hong Wang
47e689908a
spl: starfive: jh7110: switch pll2 to 1188M
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Switch the pll2 clk to 1188M with the comm pll interface on JH7110.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:38 +08:00
Yan Hong Wang
01bbc04d9d
arch: riscv: jh7110: add pll clk configuration for jh7110
...
Add common interface to set and get pll clk information for jh7110 soc.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:38 +08:00
Jianlong Huang
5ae5eca975
configs: starfive: fix tftpboot file waite a long time for the first time
...
ARP_TIMEOUT is too large, then will waite a long time for the first time
Set ARP_TIMEOUT to 500 refer to others
Set PHY_ANEG_TIMEOUT needs longer aneg time for the 2nd phy
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-10-18 16:24:38 +08:00
yanhong.wang
20f3a9aeb5
clk:jh7110: update apb_bus clk relationship
...
The previous definition of apb_bus clock relationship is incorrect,so
update it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:37 +08:00
Jianlong Huang
7cfc3f2f61
configs: starfive_evb_defconfig: Support saveenv
...
Add saveenv config to Support saveenv
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-10-18 16:24:37 +08:00
samin
0fb1b1ba81
spl:jh7110: Modify cpu frequency should be before switching pll
...
Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18 16:24:37 +08:00
Clivia.Cai
810b30254c
config:starfive-jh7110: add sd card boot config
...
Configure SD card boot parameters
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-10-18 16:24:37 +08:00
yanhong.wang
283a338dce
riscv:dts:starfive-jh7110: modify Model and riscv,isa info
...
Change Model to "StarFive JH7110 EVB", and change riscv,isa to
"rv64imafdcbsux"
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:37 +08:00
yanhong.wang
b04743f040
ram:starfive: Make ddr driver support 2G size
...
The ddr driver include two configs with 2G and 4G.Fist read the ddr size
config from the memory node in the dts,then match the right config and
do it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:37 +08:00
yanhong.wang
b8c8323ddd
reset:starfive:jh7110: Delete redundant logic
...
In the hardware design, the IPs RESET signal of jh7110 is divided into
two groups,one group is active high, and the other group is active low.
However, the software does not need to distinguish whether the RESET
signal is active high or active low,Write 1 to be assert, and write 0 to deassert.
Therefore, the software does not need to add additional logic to
distinguish these two sets of signals.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18 16:24:37 +08:00
samin
d21940b4fc
clk:jh7110: pll0 dynamically gets the frequency
...
pll0 dynamically gets the frequency.
Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18 16:24:37 +08:00
samin
66107c3e05
spl:starfive: Add support for different CPU frequencies.
...
The cpu uses 1.25G by default.
Lists of frequencies(MHz):
-375/500/625/750/875/1000/1250
-1375/1500/1625/1750/1800
Note: Some frequencies require voltage regulation.
Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18 16:24:37 +08:00
samin
90a8248c00
spl:starfive: remove function spl_cpu_fre_150/125
...
replace them with spl_cpu_set_rate.
Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18 16:24:37 +08:00