Commit graph

74867 commits

Author SHA1 Message Date
yanhong.wang
0e42aeb663 [NOT-FOR-UPSTREAM]drivers/net/phy/marvell: setup LED config for JH7100 EVB 2021-09-01 03:13:54 +08:00
TekkamanV
d26ad5ca39 [NOT-FOR-UPSTREAM]starfive: GPIO pin init
This patch should be removed, once we can do GPIO pin init
in secondboot or ddrinit
2021-09-01 03:13:54 +08:00
TekkamanV
f02cd6515b starfive: Modify designware driver for JH7100
This patch is using internal RAM to improve performance
(avoid flushing L2 cache): Modify designware driver by:
1, Modify gtxclk configuration by phydev->speed
2, Add Preseted mem support for mac descrtables and buffs
3, disable DMA memory range check when building for JH7100

The original patch is from 'Bo Li <bo.li@starfivetech.com>':
2021-09-01 03:13:54 +08:00
TekkamanV
bbb7aaa8aa starfive: fix dts(linux)
1, ccache
2, mmc
    This patch adds the necessary info for mmc driver:
    bus-width = <4>;
    max-frequency = <?0000000>;

3, uart0(console)
4, SPI Nor Flash
5, Switch dtb to linux dts
2021-09-01 03:13:54 +08:00
TekkamanV
82cc4fc313 starfive: Porting jh7100-beaglev-starlight.dts from linux
https://github.com/starfive-tech/linux/tree/beaglev
2021-09-01 03:13:54 +08:00
TekkamanV
285454ae12 starfive: Add JH7100 support
This patch adds StarFive JH7100 main support, including Starlight and EVB
support, ported from StarFive HiFive_U-Boot REPO.

    The original authors are
    bo.li <bo.li@starfivetech.com>
    Chenjieqin <Jessica.Chen@starfivetech.com>
    Huan.Feng <huan.feng@starfivetech.com>
    jack.zhu <jack.zhu@starfivetech.com>
    Jianlong Huang <jianlong.huang@starfivetech.com>
    ke.zhu <ke.zhu@starfivetech.com>
    Micheal Zhu <michael.zhu@starfivetech.com>
    Samin Guo <samin.guo@starfivetech.com>
    yanhong.wang <yanhong.wang@starfivetech.com>
    yiming.li <yiming.li@starfivetech.com>

Note:
    1, disable BTRFS(will trigger a link error with *some* RV64 GCC)
    But RV64 GCC on Fedora works well with enabling BTRFS.

    BTRFS will select ZSTD which will trigger a link error with
    *some* RV64 GCC:
    ---
    riscv64-unknown-linux-gnu-ld.bfd: /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clzsi2.o): can't link double-float modules with soft-float modules
    riscv64-unknown-linux-gnu-ld.bfd: failed to merge target specific data of file /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clzsi2.o)
    riscv64-unknown-linux-gnu-ld.bfd: /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clz.o): can't link double-float modules with soft-float modules
    riscv64-unknown-linux-gnu-ld.bfd: failed to merge target specific data of file /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clz.o)
    make: *** [Makefile:1787: u-boot] Error 1
    ---

    2, enable OF_SEPARATE:
    This is required so that openSBI can add itself to /reserved-memory, and
    let EFI know about it.

    By Andreas Schwab <schwab@suse.de>

    3, Set default fdtfile name

    By Andreas Schwab <schwab@suse.de>
2021-09-01 03:06:40 +08:00
TekkamanV
ef83c6a289 starfive: Add JH7100 MMC driver support
This driver modified from snps_dw_mmc.c

Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:43 +08:00
TekkamanV
b4d80ce599 starfive: add JH71x0 serial driver
This driver ported from NS16550 Serial Port driver, It is a simplified
version of drivers/serial/ns16550.c
We may can merge it to ns16550 later.

Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:43 +08:00
yanhong.wang
a6d542f12f starfive: add OTP driver for jh7100
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-08-31 21:06:43 +08:00
TekkamanV
99e391012d fu740: make WayEnable can be configured by menuconfig
Signed-off-by:TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:43 +08:00
TekkamanV
d7698efa3d fu740: Add flush_dcache_range function
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:43 +08:00
TekkamanV
1962f02f52 fu740: add l2cc_get_base_addr for sharing with more functions
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:43 +08:00
TekkamanV
282b348110 riscv: add reset_misc function (__weak)
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:43 +08:00
TekkamanV
8576ec63d1 riscv: Enable SYS_CLK_FREQ config
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:42 +08:00
TekkamanV
d2262f28b3 riscv: Enable SYS_MALLOC_LEN config
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:42 +08:00
TekkamanV
7bc298c771 riscv: add #define in asm/io.h for cadence_qspi_apb.c
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-08-31 21:06:42 +08:00
yanhong.wang
6b5d1e170a mtd: Add SPI Nor Flash chip GD25LQ256D ID
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-08-31 21:06:42 +08:00
Tom Rini
9b0583a839 Prepare v2021.10-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 12:45:46 -04:00
Tom Rini
18f528535d configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 12:40:24 -04:00
Tom Rini
b9cb74a5aa Xilinx changes for v2021.10-rc3
xilinx:
 - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
 - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
 - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
 
 zynq:
 - Wire single QSPI
 - Use power-source instead of io-standard properties
 - Enable nor on zc770-xm012
 
 zynqmp:
 - Change handling around multi_boot()
 - Setup offset for u-boot.itb in spi
 - Generate run time dfu_alt_info for capsule update
 - Use explicit values for enums (zynqmp_firmware.h)
 - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
 - Disable WDT driver by default
 - Bind usb/scsi via preboot because of EFI
 - DT updates/fixes
 - Add soc driver
 - Fix SPL SPI boot mode
 
 versal:
 - Add soc driver
 
 sdhci:
 - Update tap delay programming for zynq_sdhci driver
 
 cmd:
 - Fix RTC uclass handling in date command
 - Update pwm help message
 - Update reset help message
 
 watchdog:
 - Fix wwdt compilation
 
 rtc:
 - Deal with seq alias in rtc uclass
 - Add zynqmp RTC driver
 
 fdt:
 - Add kernel-doc for fdt_fixup_memory_banks()
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYSilpgAKCRDKSWXLKUoM
 Id2JAJ9jY19JiEpOd3vuRCT5CE/pzX4yDACeP8DiXDzSi5tLHwDWUCBobUTze2s=
 =5lnj
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2021.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.10-rc3

xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT

zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012

zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode

versal:
- Add soc driver

sdhci:
- Update tap delay programming for zynq_sdhci driver

cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message

watchdog:
- Fix wwdt compilation

rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver

fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
2021-08-27 08:33:02 -04:00
Michal Simek
229cb5c6ba xilinx: zynqmp: Enable stack relocation to DDR
There is no space in OCM for SPL stack because the space in OCM is occupied
by TF-A. That's why move relocate stack to DDR to 0x18000000 address
and also enable SPL_SIZE_LIMIT not to be more then 0xfffea000 which is
default address for TFA.

It is good to summarize current DDR usage in SPL flow.
0-0x80000 is used for BSS
 (CONFIG_SPL_BSS_START_ADDR, CONFIG_SPL_BSS_MAX_SIZE)
0x100000 is used for DTB passing address
 (CONFIG_XILINX_OF_BOARD_DTB_ADDR)
0x17fffe70 - CONFIG_SPL_STACK_R_ADDR - is used for GD
0x18000000 is used for SPL stack
 (CONFIG_SPL_STACK_R_ADDR)
0x20000000-0x21000000 is used for SPL malloc area
 (CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
060fa0e11b xilinx: zynqmp: Update descriptions for u-boot.its
Use TF-A instead of ATF in description. And update generic description with
removing ATF because also configurations without it are supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
52ff1626cf xilinx: common: Enabling generic function for DT reselection
U-Boot support board detection at run time and based on it change DT.
This feature is implemented for SOM Kria platforms which contain two
eeproms which contain information about SOM module and CC (Carrier card).
Full U-Boot starts with minimal DT file defined by
CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image.
It is using default setup of board_name variable initializaed to
DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option.

When DTB_RESELECT is enabled board_detection() is called. Keep it your mind
that this code is called before relocation. board_detection() is calling
xilinx_read_eeprom() which fills board_info (xilinx_board_description)
structure which are parsed in board_name_decode().
Based on DT configuration and amount of nvmemX aliases name of the board is
composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev"
<board_revision> "-" <cc_name> "-rev" <cc_revision>.

If CC is not present or more are available it keeps going.

When board name is composed and returned from board_name_decode() it is
assigned to board_name variable which is used by
board_fit_config_name_match() which is called via fdtdec_setup() when it
goes over config options in multi dtb FIT image.

From practical point of view multi DTB image is key point here which has to
contain configs for detected combinations. Unfortunately as of now they
have to be full DTBs and DTBOs are not supported.

That's why configuration like:
config_X {
	description = "zynqmp-board-cc";
	fdt = "board", "cc";
};

needs to be squashed together with:
fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \
arch/arm/dts/zynqmp-cc.dtbo

and only one dtb is in fit:
config_X {
	description = "zynqmp-board-cc";
	fdt = "board-cc";
};

For creating multi DTBs fit image use mkimage -E, e.g.:
mkimage -E -f all.its all.dtb

When DTB_RESELECT is enabled xilinx_read_eeprom() is called before
relocation and it uses calloc for getting a buffer. Because this is dynamic
memory it is not relocated that's why xilinx_read_eeprom() is called again
as the part of board_init(). This second read with calloc buffer placed in
proper position board_late_init_xilinx() can setup u-boot variables as
before.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
e69213611e xilinx: zynqmp: Generate different u-boot.itb for MULTI_DTB_FIT
When MULTI_DTB_FIT is enabled fit-dtb.blob fit image is created which
contain all DTBs listed by CONFIG_OF_LIST. And with DTB_RELESELECT there is
a need to handle it as one file with DTBs in it not as separate DTBs in
u-boot.its/itb.
That's why extend mkimage_fit_atf.sh to generate u-boot.itb correctly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
f28a22d55a arm64: dts: Make sure that all DTBs are 64bit aligned
Start of DTB should be 64bit aligned that's why also make sure that end is
also 64bit aligned. It is not required but it is nice thing to do.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
570c463680 Makefile: Align fit-dtb.blob and u-boot.itb by 64bits
Enabling MULTI_DTB_FIT and DTB_RESELECT can end up with multi DTBs in FIT
image placed and aligned only by 32bits (4bytes). Based on device tree
specification:
"Specifically, the memory reservation block shall be aligned to an 8-byte boundary
and the structure block to a 4-byte boundary."
is 64bit (8bytes) alignment required. That's why make sure that
fit-dtb.blob and u-boot.itb as our primary target images for Xilinx ZynqMP
are all 64bit aligned.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2021-08-26 08:14:43 +02:00
Michal Simek
5bd5ee02b2 xilinx: zynqmp: Check that DT is 64bit aligned
DT needs to be 64bit aligned. If it is not fdt64_to_cpu will fail when try
to read information about reserved memory. The system ends in exception
without any clue what's going it. That's why detect not aligned DT and
panic to show where the issue is coming from.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
8823253272 xilinx: Add support for generic board detection
Add support for changing DT at run time. It is done via board_detection()
which returns platform_id and platform_version which can be used via
board_name_decode() to compose board_local_name string which corresponds
with DT which is should be used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
b262863bf8 xilinx: common: Free allocated structure
There is no need to keep fru_content around. Free this space.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
d9c93c9e2c xilinx: common: Change board_info[] handling
Origin code was allocating only pointers to struct xilinx_board_description
and there was separate allocation for structure self and freeing in case of
failure.
The code is directly allocating space for all structures by one calloc to
simlify logic.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
57f710320f xilinx: Use variable for passing board_name
Use variable which points to DEVICE_TREE by default. The reason for this
change is to enable DTB_RESELECT and MULTI_DTB_FIT where board detection
can be used for change DTB at run time. That's why there must be reference
in board_fit_config_name_match() via variable instead of hardcoding it
which is sufficient for that use case.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
530560b6f8 xilinx: fru: Replace spaces with \0 in detected name
FRU spec expected \0 for unused symbols but unfortunately a lot of boards
are using spaces instead of \0. That's why after saving it to desc->name
name is checked again and all spaces are converted to \0. This will ensure
that names can be used for string manipulations like concatenation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:42 +02:00
Michal Simek
edd530651a xilinx: zynqmp: Enable gpio-key/button driver
Enable button uclass and also gpio-key driver by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:12:56 +02:00
Michal Simek
57bcae88fe arm64: zynqmp: Enable sha1sum command
Enable it for TPM usage.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Ashok Reddy Soma
e32d891659 watchdog: versal: Include header file needed for dev_ functions
dev_dbg, dev_err and dev_warn seems to be moved to different header file.
Include dm/device_compat.h file to compile properly.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
afb08a8634 xilinx: zynqmp: Add debug messages for boot mode
Add debug messages to see HW boot mode and also alternative boot mode in
logs directly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
aa5fb3de23 cmd: boot: Update reset usage message
The commit 573a3811ed ("sysreset: psci: support system reset in a generic
way with PSCI") has added support for warm reset via PSCI but this hasn't
been reflected in usage message and user has to look at the code how to run
it. That's why update usage text to make this clear.

Here is full help with updated usage:
ZynqMP> help reset
reset - Perform RESET of the CPU

Usage:
reset - cold boot without level specifier
reset -w - warm reset if implemented

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-08-26 08:08:11 +02:00
Michal Simek
a84d3b6c56 cmd: pwm: Remove additional pwm description
The first name is taken from command name that's why shouldn't be listed in
help. And commands shouldn't be listed with <> which means value but value
itself is command name.
Also add description for commands to make it clear what it does.

Before
pwm pwm <invert> <pwm_dev_num> <channel> <polarity>
pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns>
...

After:
pwm invert <pwm_dev_num> <channel> <polarity> - invert polarity
pwm config <pwm_dev_num> <channel> <period_ns> <duty_ns> - config PWM
pwm enable <pwm_dev_num> <channel> - enable PWM output
pwm disable <pwm_dev_num> <channel> - disable PWM output

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
57b2a43607 xilinx: Enable config to display cpuinfo
Enable CONFIG_DISPLAY_CPUINFO to display SoC family & revision.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
80c0d38a56 xilinx: common: Add function to print SoC info
Add print_cpuinfo() to print SoC info like family & revision.
This function depends on CONFIG_DISPLAY_CPUINFO config.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
42e20f52d9 soc: xilinx: versal: Add soc_xilinx_versal driver
soc_xilinx_versal driver allows identification of family & revision
of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL.
Probe this driver using platdata U_BOOT_DEVICE structure which is
defined at mach-versal/cpu.c.
Add this config to xilinx_versal_virt_defconfig &
xilinx_versal_mini_ospi_defconfig file to select this driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
a890a53ad2 soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
5e1a3be667 fdt_support: Add kernel-doc for fdt_fixup_memory_banks()
Add kernel-doc description for fdt_fixup_memory_banks() because it is
implemented in one specific way and this information should be available
for others to decide if their SoC conforms to it.
If you don't want U-Boot to update your memory DT layout please disable
CONFIG_ARCH_FIXUP_FDT_MEMORY.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-26 08:08:11 +02:00
Michal Simek
1031a11d71 xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.

Here is what it is happening.
Origin DT.
memory@0 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>;
};

memory@800000000 {
        device_type = "memory";
        reg = <0x8 0x00000000 0x0 0x80000000>;
};

After fdt_fixup_memory_banks()

memory@0 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};

memory@800000000 {
        device_type = "memory";
        reg = <0x8 0x00000000 0x0 0x80000000>;
};

As is visible memory@0 node got second range but there is still
memory@800000000 node present and 2G range is listed twice.

The solution can't be that second node is removed because it can be
referenced already that's why it is better for us to disable this option
for now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
c2b7244322 ARM: zynq: Enable smcc and nor for zc770-xm012
Enable cfi flash on zc770-xm012 configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
0df062bf04 ARM: zynq: Wire single qspi on couple of boards
Single configuration is working fine and no issue to enable it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Sai Krishna Potthuri
b9c4e8d439 ARM: zynq: Replace 'io-standard' with 'power-source' property
Replace 'io-standard' property with 'power-source' property in all
zynq dts files to be in sync with Zynq Pinctrl driver.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Raju Kumar Pothuraju
bc353102a0 xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)
Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatibility string to probe &
initialize flash. With missing compatibility string we are observing
below error:

Zynq> sf probe 0 0 0
 jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00  Failed to initialize SPI flash at 0:0 (error -2)

Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
1759a31288 arm64: zynqmp: Update comment style sm-k26
Trivial style patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
464f6558ca arm64: zynqmp: Fix header alignment on kv260 boards
Fix header alignment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00