Commit graph

1155297 commits

Author SHA1 Message Date
Emil Renner Berthing
0e15216a6d [NOT-FOR-UPSTREAM] Add build instructions
For convenience this also adds a small visionfive_defconfig and the
firmware needed for the brcmfmac driver along with the signed regulatory
database.

The firmware is from the linux-firmware repo and the regulatory database
from the wireless-regdb Fedora package.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
2023-02-12 23:04:43 +01:00
Fu Wei
e0f29c7e9b [NOT-FOR-UPSTREAM] riscv: Add StarFive JH7100 Fedora defconfig
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2023-02-12 23:04:43 +01:00
Emil Renner Berthing
5fffac2472 riscv: dts: Add full JH7100, Starlight and VisionFive support
Based on the device tree in https://github.com/starfive-tech/u-boot/
with contributions from:
yanhong.wang <yanhong.wang@starfivetech.com>
Huan.Feng <huan.feng@starfivetech.com>
ke.zhu <ke.zhu@starfivetech.com>
yiming.li <yiming.li@starfivetech.com>
jack.zhu <jack.zhu@starfivetech.com>
Samin Guo <samin.guo@starfivetech.com>
Chenjieqin <Jessica.Chen@starfivetech.com>
bo.li <bo.li@starfivetech.com>

Rearranged, cleanups, fixes, pins and resets added by Emil.
Cleanups, fixes, clocks added by Geert.
Cleanups and GPIO fixes from Drew.
Thermal zone added by Stephen.
PWM pins added by Jianlong.
cpu-map added by Jonas.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
2023-02-12 23:04:43 +01:00
Emil Renner Berthing
43370dd745 spi: cadence-quadspi: Allow compilation on RISC-V
This IP is also used on the StarFive JH7100 riscv64 SoC and presumably
also the upcoming JH7110 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
Farzad Farshchi
5559462ea9 nvdla: add NVDLA driver
Additional update from Prashant Gaikwad <pgaikwad@nvidia.com>
Adapted for Linux 5.13 and the BeagleV Starlight board by
<cybergaszcz@gmail.com>

kernel test robot: fix platform_no_drv_owner.cocci warnings
Geert: Use div_u64() in dla_get_time_us()

Signed-off-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20220119060057.GA1143@7f39e361da8f
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Link: https://lore.kernel.org/r/alpine.DEB.2.22.394.2203090905560.780932@ramsan.of.borg
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
sw.multimedia
e7271c9a8d drm/i2c/tda998x: Hardcode register values for Starlight
A proper solution to this hack should be found.

Signed-off-by: jack.zhu <jack.zhu@starfivetech.com>
Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
2023-02-12 23:04:43 +01:00
Emil Renner Berthing
0e279ebf6a [WIP] drm/starfive: Support DRM_FORMAT_XRGB8888
When creating dumb buffers with 32bpp and 24bit colour depth this is
default mode return by drm_mode_legacy_fb_format. So we need to support
this for common dumb buffers to just work.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
sw.multimedia
5479cd6317 drm/starfive: Add StarFive drm driver
Add starfive DRM Display driver framework

Signed-off-by: jack.zhu <jack.zhu@starfivetech.com>
Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: José Expósito <jose.exposito89@gmail.com>
Link: https://lore.kernel.org/r/a8ca722539672d6369d6e4092e1e08cb6b58c546.1645535955.git.geert@linux-m68k.org
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
Walker Chen
6337905c64 ASoC: starfive: Add StarFive JH7100 audio drivers
Signed-off-by: Michael Yan <michael.yan@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
Matteo Croce
65695561fe net: stmmac: use GFP_DMA32
Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2023-02-12 23:04:43 +01:00
Emil Renner Berthing
7c059d614b net: stmmac: Add glue layer for StarFive JH71x0 SoCs
This adds a glue layer for the Synopsys DesignWare MAC IP core on the
StarFive JH71x0 SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
Emil Renner Berthing
7ccbe80f78 dt-bindings: net: Add dwmac-starfive bindings
Add bindings for the DWMAC glue layer for the StarFive JH71x0 SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
Emil Renner Berthing
44ddbe966c net: stmmac: platform: Add snps,dwmac-5.20 IP compatible string
Add "snps,dwmac-5.20" compatible string for 5.20 version that can avoid
to define some platform data in the glue layer.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:43 +01:00
Emil Renner Berthing
4541a8c5b2 dt-bindings: net: snps,dwmac: Add dwmac-5.20 version
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
a1673b1ac3 dt-bindings: mfd: syscon: Add StarFive JH7100 sysmain compatible
Document StarFive JH7100 SoC compatible for sysmain registers.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
b0424f1c17 dt-bindings: reset: Add StarFive JH7110 always-on definitions
Add resets for the StarFive JH7110 always-on reset controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
158e7fd077 dt-bindings: reset: Add StarFive JH7110 system reset definitions
Add resets for the StarFive JH7110 system reset controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
f0bdca58f2 dt-bindings: clock: Add StarFive JH7110 always-on definitions
Add all clock outputs for the StarFive JH7110 always-on clock generator.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
f92c38a463 dt-bindings: clock: Add StarFive JH7110 system clock definitions
Add all clock outputs for the StarFive JH7110 system clock generator.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
9e36e0761a net: phy: motorcomm: Disable rgmii rx delay
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2023-02-12 23:04:42 +01:00
Samin Guo
282e33840d dmaengine: dw-axi-dmac: Add StarFive JH7100 support
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Samin Guo
55d5f5d828 dmaengine: dw-axi-dmac: Handle xfer start while non-idle
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
2023-02-12 23:04:42 +01:00
Geert Uytterhoeven
e045c0a44d [WIP] dt-bindings: dma: dw-axi-dmac: Increase DMA channel limit to 16
The first DMAC instance in the StarFive JH7100 SoC supports 16 DMA
channels.

FIXME Given there are more changes to the driver than just increasing
      DMAC_MAX_CHANNELS, we probably need a new compatible value, too.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2023-02-12 23:04:42 +01:00
Chenjieqin
a5c8f96c3a pwm: sifive-ptc: Add SiFive PWM PTC driver
yiming.li: clear CNTR of PWM after setting period & duty_cycle
Emil: cleanups, clock, reset and div_u64

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Samin Guo
0f35c858ed drivers/tty/serial/8250: update driver for JH7100 2023-02-12 23:04:42 +01:00
Emil Renner Berthing
541a0cc43d power: reset: tps65086: Allow building as a module
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
7735322fcf riscv: Implement non-coherent DMA support via SiFive cache flushing
This variant is used on the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:42 +01:00
Emil Renner Berthing
4dee2cd243 soc: sifive: ccache: Add non-coherent DMA handling
Add functions to flush the caches and handle non-coherent DMA.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-12 23:04:41 +01:00
Cristian Ciocaltea
944a2191d3 dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property
Add the 'uncached-offset' property to be used for specifying the
uncached memory offset required for handling non-coherent DMA
transactions.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230211031821.976408-3-cristian.ciocaltea@collabora.com
2023-02-12 23:04:41 +01:00
Emil Renner Berthing
0e409232a9 soc: sifive: ccache: Add StarFive JH71x0 support
This adds support for the StarFive JH7100 and JH7110 SoCs which also
feature this SiFive cache controller.

Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:19:49 +01:00
Emil Renner Berthing
978c0ca11f dt-bindings: riscv: sifive-ccache: Support StarFive JH71x0 SoCs
This cache controller is also used on the StarFive JH7100 and JH7110
SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:32 +01:00
Huan Feng
d07cdb8756 hwrng: Add StarFive JH7100 Random Number Generator driver
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:32 +01:00
Samin Guo
318fbe3674 watchdog: Add StarFive SI5 watchdog driver
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:32 +01:00
Emil Renner Berthing
4985191bb6 hwmon: (sfctemp) Add StarFive JH71x0 temperature sensor
Register definitions and conversion constants based on sfctemp driver by
Samin in the StarFive 5.10 kernel.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-02-11 15:16:32 +01:00
Emil Renner Berthing
e703d61fd9 dt-bindings: hwmon: add starfive,jh71x0-temp bindings
Add bindings for the temperature sensor on the StarFive JH7100 and
JH7110 SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:32 +01:00
Emil Renner Berthing
34de3d2044 serial: 8250_dw: Add starfive,jh7100-hsuart compatible
This adds a compatible for the high speed UARTs on the StarFive JH7100
RISC-V SoC. Just like the regular uarts we also need to keep the input
clocks at their default rate and rely only on the divisor in the UART.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:32 +01:00
Emil Renner Berthing
2a335d2004 pinctrl: starfive: Reset pinmux settings
Current u-boot doesn't seem to take into account that some GPIOs are
configured as inputs/outputs of certain peripherals on power-up. This
means it ends up configuring some GPIOs as inputs to more than one
peripheral which the documentation explicitly says is illegal. Similarly
it also ends up configuring more than one GPIO as output of the same
peripheral. While not explicitly mentioned by the documentation this
also seems like a bad idea.

The easiest way to remedy this mess is to just disconnect all GPIOs from
peripherals and have our pinmux configuration set everything up
properly. This, however, means that we'd disconnect the serial console
from its pins for a while, so add a device tree property to keep
certain GPIOs from being reset.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:32 +01:00
Emil Renner Berthing
cfa948332f clk: starfive: jh7100: Keep more clocks alive
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:32 +01:00
Emil Renner Berthing
507a643dd6 RISC-V: Add StarFive JH7100 audio reset node
Add device tree node for the audio resets on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Emil Renner Berthing
3da1f02ce9 reset: starfive: Add JH7100 audio reset driver
The audio resets are almost identical to the system resets, there are
just fewer of them. So factor out and export a generic probe function,
so most of the reset controller implementation can be shared.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Emil Renner Berthing
144a69d2cd reset: starfive: Use 32bit I/O on 32bit registers
The driver currently uses 64bit I/O on the 32bit registers. This works
because there are 4 assert registers and 4 status register, so they're
only ever accessed on 64bit boundaries.

There are however other reset controllers for audio and video on the SoC
with only one status register that isn't 64bit aligned so 64bit I/O
would result in an unaligned access exception.

Switch to 32bit I/O in preparation for supporting these resets too.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Emil Renner Berthing
76448b8776 reset: Create subdirectory for StarFive drivers
This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Emil Renner Berthing
be143f2347 dt-bindings: reset: Add starfive,jh7100-audrst bindings
Add bindings for the audio reset controller on the StarFive JH7100
RISC-V SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Emil Renner Berthing
a3efd0b92b dt-bindings: reset: Add StarFive JH7100 audio reset definitions
Add all resets for the StarFive JH7100 audio reset controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Emil Renner Berthing
5222afd64e RISC-V: Mark StarFive JH7100 as having non-coherent DMAs
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Emil Renner Berthing
484ef7ec50 RISC-V: Add StarFive JH7100 audio clock node
Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Geert Uytterhoeven
003c3800d8 riscv: dts: starfive: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.

Fix this by grouping the tuples of "interrupts-extended" properties
using angle brackets.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2023-02-11 15:16:31 +01:00
Matteo Croce
1869f27c9f riscv: optimized memset
The generic memset is defined as a byte at time write. This is always
safe, but it's slower than a 4 byte or even 8 byte write.

Write a generic memset which fills the data one byte at time until the
destination is aligned, then fills using the largest size allowed,
and finally fills the remaining data one byte at time.

Signed-off-by: Matteo Croce <mcroce@microsoft.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00
Matteo Croce
0bdabfc1f1 riscv: optimized memmove
When the destination buffer is before the source one, or when the
buffers doesn't overlap, it's safe to use memcpy() instead, which is
optimized to use a bigger data size possible.

Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2023-02-11 15:16:31 +01:00
Matteo Croce
af5a304a0b riscv: optimized memcpy
Write a C version of memcpy() which uses the biggest data size allowed,
without generating unaligned accesses.

The procedure is made of three steps:
First copy data one byte at time until the destination buffer is aligned
to a long boundary.
Then copy the data one long at time shifting the current and the next u8
to compose a long at every cycle.
Finally, copy the remainder one byte at time.

On a BeagleV, the TCP RX throughput increased by 45%:

before:

$ iperf3 -c beaglev
Connecting to host beaglev, port 5201
[  5] local 192.168.85.6 port 44840 connected to 192.168.85.48 port 5201
[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
[  5]   0.00-1.00   sec  76.4 MBytes   641 Mbits/sec   27    624 KBytes
[  5]   1.00-2.00   sec  72.5 MBytes   608 Mbits/sec    0    708 KBytes
[  5]   2.00-3.00   sec  73.8 MBytes   619 Mbits/sec   10    451 KBytes
[  5]   3.00-4.00   sec  72.5 MBytes   608 Mbits/sec    0    564 KBytes
[  5]   4.00-5.00   sec  73.8 MBytes   619 Mbits/sec    0    658 KBytes
[  5]   5.00-6.00   sec  73.8 MBytes   619 Mbits/sec   14    522 KBytes
[  5]   6.00-7.00   sec  73.8 MBytes   619 Mbits/sec    0    621 KBytes
[  5]   7.00-8.00   sec  72.5 MBytes   608 Mbits/sec    0    706 KBytes
[  5]   8.00-9.00   sec  73.8 MBytes   619 Mbits/sec   20    580 KBytes
[  5]   9.00-10.00  sec  73.8 MBytes   619 Mbits/sec    0    672 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.00  sec   736 MBytes   618 Mbits/sec   71             sender
[  5]   0.00-10.01  sec   733 MBytes   615 Mbits/sec                  receiver

after:

$ iperf3 -c beaglev
Connecting to host beaglev, port 5201
[  5] local 192.168.85.6 port 44864 connected to 192.168.85.48 port 5201
[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
[  5]   0.00-1.00   sec   109 MBytes   912 Mbits/sec   48    559 KBytes
[  5]   1.00-2.00   sec   108 MBytes   902 Mbits/sec    0    690 KBytes
[  5]   2.00-3.00   sec   106 MBytes   891 Mbits/sec   36    396 KBytes
[  5]   3.00-4.00   sec   108 MBytes   902 Mbits/sec    0    567 KBytes
[  5]   4.00-5.00   sec   106 MBytes   891 Mbits/sec    0    699 KBytes
[  5]   5.00-6.00   sec   106 MBytes   891 Mbits/sec   32    414 KBytes
[  5]   6.00-7.00   sec   106 MBytes   891 Mbits/sec    0    583 KBytes
[  5]   7.00-8.00   sec   106 MBytes   891 Mbits/sec    0    708 KBytes
[  5]   8.00-9.00   sec   106 MBytes   891 Mbits/sec   28    433 KBytes
[  5]   9.00-10.00  sec   108 MBytes   902 Mbits/sec    0    591 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.00  sec  1.04 GBytes   897 Mbits/sec  144             sender
[  5]   0.00-10.01  sec  1.04 GBytes   894 Mbits/sec                  receiver

And the decreased CPU time of the memcpy() is observable with perf top.
This is the `perf top -Ue task-clock` output when doing the test:

before:

Overhead  Shared O  Symbol
  42.22%  [kernel]  [k] memcpy
  35.00%  [kernel]  [k] __asm_copy_to_user
   3.50%  [kernel]  [k] sifive_l2_flush64_range
   2.30%  [kernel]  [k] stmmac_napi_poll_rx
   1.11%  [kernel]  [k] memset

after:

Overhead  Shared O  Symbol
  45.69%  [kernel]  [k] __asm_copy_to_user
  29.06%  [kernel]  [k] memcpy
   4.09%  [kernel]  [k] sifive_l2_flush64_range
   2.77%  [kernel]  [k] stmmac_napi_poll_rx
   1.24%  [kernel]  [k] memset

Signed-off-by: Matteo Croce <mcroce@microsoft.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-02-11 15:16:31 +01:00